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    2,000 verilog vhdl vergleich jobs found, pricing in GBP
    you must have ( BCU1525 device) for FPGA Bitstream development pro .,.,.,. Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £830 (Avg Bid)
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    Redesign custom search page, implement/copy all necessary css, jquery from extern page (not mine) -- 2 Ended

    Hi there, I am searching someone experienced who can implement all click and hover functions like the opening of tabs, popover etc. NO BOOTSTRAP ALLOWED! Neither Bootstrap CSS or Bootstrap jQuery is allowed. Here is the example how the single entry should look like: The task is that the search container on my page in production: http://45.32.239

    CSS HTML jQuery / Prototype PHP Website Design
    £129 (Avg Bid)
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    Implementation of keccak256 algorithm Ended

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with ; a. The source can be taken as MVis-tokenminer 2.1.17; 2. The basis of the hash function is to take the source code ; a. The keccak256 algorithm should operate at the maximum FPGA frequency xcku035-1ffva1156c; b. The algorithm must use a minimum of LUT; c. The algorithm must use DSP Slices and Block RAM; d. The number of streams (copies of the algorithm) should be limited

    Electronics FPGA Matlab and Mathematica Verilog / VHDL
    £494 (Avg Bid)
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    find fpga projects Ended

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    Electrical Engineering Electronics FPGA Verilog / VHDL
    £352 (Avg Bid)
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    4 bit alu implemenation Ended

    need report on vhdl of 4 bit alu

    C++ Programming Electrical Engineering Engineering FPGA Verilog / VHDL
    £73 (Avg Bid)
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    22 bids
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    coding in vhdl - 07/01/2019 21:26 EST Ended

    Hi,eveyone.I need a signal processing coding for my work using altra quartus II and VHDL.

    Electrical Engineering FPGA Verilog / VHDL
    £76 (Avg Bid)
    NDA
    £76 Avg Bid
    6 bids
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    Matlab Codnig Ended

    I need the matlab developer and verilog developer

    Electrical Engineering LabVIEW Matlab and Mathematica Software Architecture Verilog / VHDL
    £436 (Avg Bid)
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    16 bids
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    implementation of 4 bit alu Ended

    Implementation of 4 bit alu in VHDL using the software Xillinix ISE I Need report on circuits diagrams, truth table, and simulations results the structure report should go by 1-introduction 2-block diagram 3-Technical Words 4-Implementations 5-Results 6-Conclusion

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    £96 (Avg Bid)
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    5 bids
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    Redesign custom search page, implement/copy all necessary css, jquery from extern page (not mine) Ended

    Hi there, I am searching someone experienced who can implement all click and hover functions like the opening of tabs, popover etc. NO BOOTSTRAP ALLOWED! Neither Bootstrap CSS or Bootstrap jQuery is allowed. Here is the example how the single entry should look like: The task is that the search container on my page in production: http://45.32.239

    CSS HTML jQuery / Prototype PHP Website Design
    £136 (Avg Bid)
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    15 bids
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    16-point FFT Ended

    verilog code for radix-4 16 point fft

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    £11 (Avg Bid)
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    6 bids
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    FFT working in VHDL Ended

    I want a VHDL code to achieve a N point FFT

    C++ Programming Electrical Engineering FPGA Matlab and Mathematica Verilog / VHDL
    £104 (Avg Bid)
    £104 Avg Bid
    12 bids
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    verilog coding for radix-4 16 point fft Ended

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    Matlab and Mathematica Verilog / VHDL
    £12 (Avg Bid)
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    2 bids
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    Trophy icon Explanation of VHDL code Ended

    I have a VHDL code.. I need someone to explain that code in detail to me.. what stuff it is doing on board..

    C Programming C++ Programming Electrical Engineering FPGA Verilog / VHDL
    £8 (Avg Bid)
    Guaranteed
    £8
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    you must have ( BCU1525 device) for FPGA Bitstream development pro Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £9249 (Avg Bid)
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    Project for Ahmed M. -- 6 Ended

    Hi Ahmed M., Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verified on ILA in Hz. Also comment every line of code.

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    £39 / hr (Avg Bid)
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    you must have ( BCU1525 device) for FPGA Bitstream development task Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £706 - £706
    £706 - £706
    0 bids
    Bid now
    Project of BCU1525 for FPGA Bitstream development task Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £718 - £724
    £718 - £724
    0 bids
    Bid now
    Project of BCU1525 for FPGA Bitstream development Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £706 - £707
    £706 - £707
    0 bids
    Bid now
    BCU1525 for FPGA Bitstream development work Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £706 - £706
    £706 - £706
    0 bids
    Bid now
    Project for Ahmed M. -- 18/12/26 18:10:58 Ended

    Initial Milestone : Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verif on ILA

    Arduino Digital Design Electronics FPGA LabVIEW
    £138 (Avg Bid)
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    BCU1525 for FPGA Bitstream development .,., Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £686 (Avg Bid)
    £686 Avg Bid
    2 bids
    Bid now
    BCU1525 for FPGA Bitstream development Ended

    Please read all the details first. an...milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting with (Equihash Varient or X16r (required chaining 2 together)? have you developed bistreams before? Please check all more details on word ...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £589 - £706
    £589 - £706
    0 bids
    Bid now
    Private project or contest #18415312 Ended

    Please Sign Up or Login to see details.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    Sealed
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    Project for Ahmed M. Ended

    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I'm a friend of Alessandro that contact you for a mini project of VHDL

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    £40 (Avg Bid)
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    1 bids
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    Vhdl UART communication code Ended

    Hello That I want is a basic uart communication with fifo buffer I have a small code ready At last I want a small call for explain

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £47 (Avg Bid)
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    3 bids
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    reviewing a code Ended

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

    Digital Design Electrical Engineering Electronics Verilog / VHDL
    £41 (Avg Bid)
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    1 bids
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    LUT optimization of FFT Ended

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    FPGA Verilog / VHDL Very-large-scale integration (VLSI)
    £106 (Avg Bid)
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    6 bids
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    SPI Master Ended

    I want SPI master in VHDL for writing and reading from flash IS25WP032

    Assembly C Programming Engineering Microcontroller Verilog / VHDL
    £152 (Avg Bid)
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    11 bids
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    Verilog Expert Ended

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    £44 (Avg Bid)
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    18 bids
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    Design 4 bit Adder in Verilog Ended

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    Verilog / VHDL
    £28 (Avg Bid)
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    5 bids
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    VHDL FPGA Project Ended

    This Project focuses on the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to the real as possible, but in a controlled environment with a simple design. Requirements • To know the general characteristics and tools involved in the design process of a specific application integrated circuit (ASIC), specifically a FPGA. • Know how to implement logical functions in programmable logical devices using description languages of Hardware, in particular, VHDL. • Know how to design on FPGAs using spe...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £626 (Avg Bid)
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    Vhdl project Ended

    It is a cluster related vhdl project.

    C Programming Electrical Engineering Engineering FPGA Verilog / VHDL
    £250 (Avg Bid)
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    9 bids
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    Development of hardware solutions on CPU, GPU & FPGA for 2-D Phase Unwrapping algorithm Ended

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comparing MATLAB result with Xilinx@ System Generator result for above specified 3 images with different sources of errors like noise, under sampling & phase abrupt changes.

    Engineering Matlab and Mathematica Verilog / VHDL
    £96 (Avg Bid)
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    VHDL FPGA GAME IMPLEMENTATION Ended

    VHDL implemented in altera de2 board

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £178 (Avg Bid)
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    QUARTUS II (ALTERA DE2 - FPGA VHDL) Ended

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £88 (Avg Bid)
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    write vhdl code for a simple basic processor with control unit Ended

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    Electronics FPGA Microcontroller Verilog / VHDL
    £18 (Avg Bid)
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    multi level parking system by using VERILOG in Xilinks and Nexys2 FPGA -- 2 Ended

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking according to the color, then in the monitor it will show how many total vacant and occupied parking lots and it will show where should the car park...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £69 (Avg Bid)
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    5 bids
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    Verilog Phase Locked Loop Simulation Ended

    Verilog Phase Locked Loop Simulation

    Computer Science Electrical Engineering Mathematics Matlab and Mathematica Verilog / VHDL
    £18 (Avg Bid)
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    Verilog simulation of two action-reaction processes Ended

    Verilog simulation of two action-reaction processes

    Digital Design Electrical Engineering Electronic Design Mathematics Verilog / VHDL
    £23 (Avg Bid)
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    6 bids
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    multi level parking system by using VERILOG in Xilinks and Nexys2 FPGA Ended

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking according to the color, then in the monitor it will show how many total vacant and occupied parking lots and it will show where should the car park...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £140 (Avg Bid)
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    Project for Zain A. -- 18/12/09 13:20:26 Ended

    6 Vhdl questions to solve

    Algorithm AutoCAD C Programming CAD/CAM Chemical Engineering
    £8 (Avg Bid)
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    Anyone expert in vhdl Ended

    Vhdl is needed

    Verilog / VHDL
    £21 (Avg Bid)
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    6 bids
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    FPGA Verilog Programming Ended

    Need help program FPGA with Artix-7 using Verliog.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £117 (Avg Bid)
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    3 bids
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    Hardware Engineer - 08/12/2018 07:24 EST Ended

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £15 / hr (Avg Bid)
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    2 bids
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    VHDL code that reads 3 txt file and produce 3 txt file Ended

    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

    C++ Programming Electrical Engineering FPGA Matlab and Mathematica Verilog / VHDL
    £29 (Avg Bid)
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    Urgent FPGA Verilog Project Help Ended

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    £138 (Avg Bid)
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    1 bids
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    Zen Protocol Miner in Verilog/VHDL Ended

    Implement the Zen Protocol in the FPGA and update the Mining App

    C Programming Engineering FPGA Microcontroller Verilog / VHDL
    £963 (Avg Bid)
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    VHDL game using LED and 7-Segment Ended

    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the LED right.

    FPGA Microcontroller Verilog / VHDL
    £13 / hr (Avg Bid)
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    questions Verilog or System Verilog questions. Ended

    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions …)

    C Programming Electrical Engineering Engineering FPGA Verilog / VHDL
    £18 (Avg Bid)
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    Make a serial interface system using Verilog Ended

    Make a serial interface system using Verilog

    Verilog / VHDL
    £54 (Avg Bid)
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