Verilog / VHDL Jobs

I want to Hire I want to Work
About Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    Apply Filter
    16 jobs found, pricing in GBP
    Design and verification of MBIST inserted dual port ram 6 days left

    Designing a dual port ram module and then instanciating this module to the BIST [login to view URL] this MBIST inserted rtl using UVM methodology

    Front-end Design Simulation Verilog / VHDL Very-large-scale integration (VLSI)
    £15 - £122
    £15 - £122
    0 bids
    Bid now
    Modification for verilog 6 days left

    A verilog model needs to be modified to some requirements

    Circuit Design Digital ASIC Coding Electrical Engineering FPGA Coding Verilog / VHDL
    £18 (Avg Bid)
    £18 Avg Bid
    4 bids
    Bid now
    Design and verification of MBIST inserted dual port ram 5 days left

    Design of dual port ram having each port with different clocks and write enable of 4 [login to view URL] the 23 states marching algorithm of the bist controller rtl this dual port ram should be instantiated then for this module verifcation should be done using UVM methodology or system verilog .with the insertion of MBIST how the verfication must be done for memory module

    Front-end Design Simulation Verilog / VHDL Very-large-scale integration (VLSI)
    £6 - £15
    £6 - £15
    0 bids
    Bid now
    Development of SPI verification IP using UVM 5 days left

    should develop SPI single master-single slave verification IP using UVM and verify different test scenarios. should mimic the BFM design in driver without using DUT and verify all the modes of SPI and some error conditions and create coverage statistics for the verified module.

    Front-end Design Simulation Verilog / VHDL Very-large-scale integration (VLSI)
    £6 - £15
    £6 - £15
    0 bids
    Bid now
    Hybrid DC Circuit Breaker with Fault-Current-Limiting Capability for 2 terminal 2 level VSC-HVDC Transmission System using PSCAD 4 days left

    need to design a 2 terminal 2 level VSC-HVDC Transmission system with a DC circuit breaker series will an FCLC (fault current limiting circuit).

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    £140 (Avg Bid)
    £140 Avg Bid
    2 bids
    Bid now
    Verification of MESI protocol using System Verilog and UVM 4 days left

    MESI is a cache coherence protocol. The verification of the protocol is to be done using System Verilog and UVM. The signals to verify is sent through the sequencer to the driver and through the virtual interface to the DUT. The assertion checks should be written in the testbench.

    Front-end Design Simulation Verilog / VHDL Very-large-scale integration (VLSI)
    £19 (Avg Bid)
    £19 Avg Bid
    1 bids
    Bid now
    Advanced Serial Communication between PC-FPGA 3 days left

    I want to send data from FPGA to PC at high speed.

    C Programming C++ Programming Serial Peripheral Interface (SPI) Verilog / VHDL
    £203 (Avg Bid)
    £203 Avg Bid
    8 bids
    Bid now
    Looking for an Xilinx vivado FPGA programming and Matlab HDL coder expert. 2 days left
    VERIFIED

    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

    Embedded Software FPGA Matlab and Mathematica Telecommunications Engineering Verilog / VHDL
    £14 / hr (Avg Bid)
    £14 / hr Avg Bid
    6 bids
    Bid now
    Bitcoin miner 2 days left
    VERIFIED

    Bit coins miner prototype required for 1 ph/s

    ASIC Bitcoin FPGA Verilog / VHDL
    £10745 (Avg Bid)
    £10745 Avg Bid
    4 bids
    Bid now
    VLSI Project -- 3 2 days left
    VERIFIED

    Looking for someone with experience in VLSI and the cadence virtuoso software. Need to implement a certain function in hardware. Please let me know if you are interested and we can discuss more. Thanks

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    £98 (Avg Bid)
    £98 Avg Bid
    12 bids
    Bid now
    To simulate RTL Design of GCD of two numbers in Verilog using Xilinx ISE. 1 day left
    VERIFIED

    Design a GCD for two 4-bit numbers (in your lecture notes, we have already done this). It will output the binary value of the greatest common divisor of those two 4-bit numbers.

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    £21 (Avg Bid)
    £21 Avg Bid
    7 bids
    Bid now
    Algorithm Design 1 day left

    Need an algorithm designer using Brute force and Divide and conquer methods in Computer science C language

    Algorithm C Programming C++ Programming Software Architecture Verilog / VHDL
    £67 (Avg Bid)
    £67 Avg Bid
    9 bids
    Bid now
    FPGA implementation of Spiking neural network using HLS 1 day left

    Request details FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.

    C Programming C++ Programming LabVIEW Microcontroller Verilog / VHDL
    £474 (Avg Bid)
    £474 Avg Bid
    5 bids
    Bid now
    FPGA implementation of Spiking neural network using HLS 1 day left

    FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.

    C Programming C++ Programming LabVIEW Microcontroller Verilog / VHDL
    £179 (Avg Bid)
    £179 Avg Bid
    1 bids
    Bid now
    merge sort using cuda on nvidia gpu and modelsim design 12 hours left

    i need an expert who can help in creating merge sort algorithm using cuda and nvidia gpu and also formula design in modelsim more details in the inbox

    CUDA Electrical Engineering GPGPU Machine Learning (ML) Verilog / VHDL
    £142 (Avg Bid)
    £142 Avg Bid
    6 bids
    Bid now
    Direct Digital Frequency Synthesizer Ending left

    vhdl/verilog code for direct digital frequency synthesizer based on look up table method.

    Analog Electronics FPGA Coding MATLAB Verilog / VHDL Very-large-scale integration (VLSI)
    £9 (Avg Bid)
    £9 Avg Bid
    3 bids
    Bid now
    Showing 1 to 16 of 16 entries
    Results per page