Designing a dual port ram module and then instanciating this module to the BIST [login to view URL] this MBIST inserted rtl using UVM methodology
Design of dual port ram having each port with different clocks and write enable of 4 [login to view URL] the 23 states marching algorithm of the bist controller rtl this dual port ram should be instantiated then for this module verifcation should be done using UVM methodology or system verilog .with the insertion of MBIST how the verfication must be done for memory module
should develop SPI single master-single slave verification IP using UVM and verify different test scenarios. should mimic the BFM design in driver without using DUT and verify all the modes of SPI and some error conditions and create coverage statistics for the verified module.
need to design a 2 terminal 2 level VSC-HVDC Transmission system with a DC circuit breaker series will an FCLC (fault current limiting circuit).
MESI is a cache coherence protocol. The verification of the protocol is to be done using System Verilog and UVM. The signals to verify is sent through the sequencer to the driver and through the virtual interface to the DUT. The assertion checks should be written in the testbench.
I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...
Design a GCD for two 4-bit numbers (in your lecture notes, we have already done this). It will output the binary value of the greatest common divisor of those two 4-bit numbers.
Request details FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.
FPGA implementation of Neural Network, using Vivado HLS, on the PYNQ board. The python code is available. Need someone know how to write this code in C or C++ and then implement it on FPGA using HLS. The python code and paper are available.
i need an expert who can help in creating merge sort algorithm using cuda and nvidia gpu and also formula design in modelsim more details in the inbox