Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers


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    214 jobs found, pricing in GBP

    Choose an algorithm of Random Number Generator and develope high-performance computing architecture of the chosen algorithm using the Electronic Design Automation tools. Write a program and integrate with a hpc scheme simulator.

    £87 (Avg Bid)
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    8 bids

    Hello, I need a controller for a MAX31855 in Verilog. The controller must be connected to an UART in order to see the data in a terminal. FPGA clock is 50Mhz.

    £52 (Avg Bid)
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    5 bids

    UVM testbench architecture for a synchronous FIFO.

    £29 (Avg Bid)
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    6 bids

    Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision. The Reed Solomon En/Decoder...

    £461 (Avg Bid)
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    11 bids
    Rework of PLC & HMI program 4 days left

    Hello, We want to modify/rework on process of existing PLC & HMI Program built by one freelancer. We will provide previous & new process details, also we will provide program built by freelancer.

    £307 (Avg Bid)
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    19 bids

    Implement the 4-way handshaking protocol by using SC_METHOD

    £55 (Avg Bid)
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    2 bids

    A Signal Generator should be programmable. A user can use the LCD display and the keyboard to change the: Frequency scale Amplitude scale offset on/off etc.

    £15 (Avg Bid)
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    12 bids

    A (PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK, OQPSK, 8-PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selec...

    £470 (Avg Bid)
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    16 bids

    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

    £149 (Avg Bid)
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    7 bids
    MPI Project Expert Needed 1 day left

    MPI Project Expert Needed Regular Work

    £106 (Avg Bid)
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    5 bids

    i have got XY table with two stepper motors. need a code to drive these motors to plot a circle. microcontroler used is atmega8

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    10 bids

    A stepper motor controller in verilog ,

    £136 (Avg Bid)
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    15 bids
    vhdl expert needed3 15h left

    Expert in VHDL is needed to do a project

    £19 (Avg Bid)
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    8 bids

    Design software and hardware for measuring voltage, amperage, rpm, temperature, pressure using the "National Instruments Labview.

    £367 (Avg Bid)
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    19 bids

    hello how are you see below text if there are available, find the best tell me at least 1 prominent and 1 complimentary alternative spare the second source which group of two is the best Flow Method IDE ( for below ) ======================= Task#01: research for IOT IDE, ...

    £20 (Avg Bid)
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    7 bids

    How much it would cost and how much time it may take to build the one shown in link below [url removed, login to view]

    £82 (Avg Bid)
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    2 bids

    I require you to do implementation of ANN or SVM algorithm in Arduino Microcontroller for 1-D EEG signal.

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    12 bids

    PID Controller Using Particle Swarm Optimization (PSO) for DC-DC converter design a PID Controller using PSO algorithm

    £87 (Avg Bid)
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    16 bids
    MIPS project123 Ended

    MIPS code and assembly language

    £11 (Avg Bid)
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    1 bids

    • Target DDR3 controllers development for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document

    £1599 (Avg Bid)
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    7 bids