build me a Verilog code -- 2

hi, I am a senior digital design engineer, I have a wide knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using modelsim, Vivado, ISE and Quartise. I will provide you a professional report about your project with citation and scientific formatting. Please contact me to know more about your needs. Regards, moaaz.

i have 2.5+ year experience in design and verification, i have done 30+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support after completion of project, thanks and regard kundan vaghela

Hello, I have experience with verilog and FPGAs and I can help you with this project if you haven’t found anyone yet.

I had already done with this counter project with its verification. Cost is 1 dollar for entire counter project. My email id is saurabhsinghn1998