1. Write a netlist for a a 3 bit adder, size, test and verify its functionality in LTspice using a local 25IF
2. Implement the 3-bit adder layout in LASI7. The layout must be DRC clean and the netlist created from the layout should pass the functionality test.
Deadline Wednesday 3 pm (Eastern time, New York time)
Can you do it please?
developer of electronic prototypes Hi, I'm, I have enough experience with LTspice I see that your project is very urgent need for today
I can start working right now