Coding in SystemVerilog and UVM

Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. We have a team of 4 members who are well qualified and highly experienced in VLSI codding and simu More

Please visit my profile to see my experience over this project

Hello! Please check my reviews to know a bit about me. It would be great if I COULD help you out. Thank you

Hi I have 5 year experience in Design verification (IP SOC level)& expertise in System Verilog and UVM. I can work on this project efficiently

Hi, I am an ASIC Design Verification Engineer fully employed for one consult company that have been working with mayor market players in ASIC. I have more than 3years knowledge in Verilog ASIC Design, a year in More

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Hello, I'm an experienced IC design engineer and I can help in achieving what is required. For further information about me, please check my LinkedIn profile "Fathi Layouni". So please feel free to contact me in More

I have worked in Mentor Graphics Egypt in The Hardware verification department, i worked on testing and verification of memory softmodels, memories (DDR3, LPDDR3, DDR4, LPDDR4). I worked using Mentor simulation tool More

I worked in multiple international companies.I have long experience in system verilog and good experience in UVM/OVM in sequences and drivers and monitors and make coverage groups for the bins that we want to see its c More

Hi, I have more than 10.5+ years of experience in the field of Digital Verification using Verilog, SystemVerilog and UVM and various industry level protocols. Please share the protocol for which you are looking forw More

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Consulting also on design and testbench structures

I have 3 years of experience in asic verification and my technical skills are listed below. Key Skills • Languages : System Verilog, Verilog • Scripting : Linux Shell scripting • Version-control : SVN,P More