E1 framer verilog jobs

I want to Hire I want to Work

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    Apply Filter
    2,000 e1 framer verilog jobs found, pricing in GBP
    verilog easy project Ended

    I need help with verilog project no more than $30 please

    Electrical Engineering Verilog / VHDL
    £21 (Avg Bid)
    £21 Avg Bid
    16 bids
    Bid now
    Need TM and ASM Ended

    I am looking for a freelancer to help me with my project. The skills required are C# Programming, C++ Programming, LabVIEW and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

    C# Programming C++ Programming LabVIEW Verilog / VHDL
    £278 (Avg Bid)
    £278 Avg Bid
    5 bids
    Bid now
    Verilog / VHDL experenced required -- 2 Ended

    I need a VHDL experienced expert for my multiple projects. If you have knowledge please bid. Details will be shared in message with the freelancers.

    Verilog / VHDL
    £5 - £15
    Sealed
    £5 - £15
    40 bids
    Bid now
    Writing a verification plan for a Design under test in system verilog -- Project for punamsengupta Ended

    The project is to come up with verification plan and write test cases to test it.

    Verilog / VHDL
    £122 (Avg Bid)
    £122 Avg Bid
    3 bids
    Bid now
    Field Programable Gate Arrays Ended

    (chane it from VHDL to verilog )the sol is the old one which in VHDL with the solution i need the sulotion for verilog

    Digital Design
    £37 (Avg Bid)
    £37 Avg Bid
    7 bids
    Bid now
    Design, simulate, and implement new instructions for the Simple Computer from a specification. Write a report describing the design process and its results. Ended

    ...Write a report describing the design process and its results. The Simple Computer from Chapter 8 of the textbook is a single‐cycle, load‐store central processing unit (CPU). The singlecycle Simple Computer illustrates many of the major principles and design constraints involved in implementing a CPU. For this project, you will trace the execution of a small program on the Simple Computer in a Verilog simulation. You will then modify the design of the Simple Computer to include several new instructions and demonstrate the correct operation of those instructions in simulation and on the DE0 Nano board. Table 1 shows the new instructions that you must implement in the Simple Computer, along with one optional instruction for extra credit. Table 1 shows similar information for ...

    Circuit Design Electrical Engineering Engineering Verilog / VHDL
    £137 (Avg Bid)
    £137 Avg Bid
    8 bids
    Bid now
    verilog project Ended

    I need help with verilog project,

    Electrical Engineering English (US) Translator Verilog / VHDL
    £24 (Avg Bid)
    £24 Avg Bid
    15 bids
    Bid now
    matlab project Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

    Matlab and Mathematica
    £139 (Avg Bid)
    £139 Avg Bid
    7 bids
    Bid now
    post a project - 08/04/2017 16:34 EDT Ended

    I need a specification document for my micro project in verilog.

    Verilog / VHDL
    £20 (Avg Bid)
    £20 Avg Bid
    6 bids
    Bid now
    post a project - 08/04/2017 16:34 EDT Ended

    I need a specification document for my micro project in verilog.

    Verilog / VHDL
    £20 (Avg Bid)
    £20 Avg Bid
    5 bids
    Bid now
    Alter pictures Ended

    I have a combinations of 5 photos to create/modify 1-The first one would be a a picture of the beach with directional signs of specific country on it example: 2- Adapt a picture of a gifted box by a black box on this picture: 3- edit of a polaroid wall to insert pictures in it: (edited).jpg 4- Insert a picture on the screen of the laptop in this picture: 5-change the box to a black box on the picture below: https://thumb9

    Photo Editing Photoshop Photoshop Design
    £50 (Avg Bid)
    £50 Avg Bid
    34 bids
    Bid now
    vhdl traffic light controller Ended

    I am looking for a freelancer to help me with my project. The skills required are FPGA, I Verilog / VHDL. I am happy to pay a fixed priced and my budget is $20 CAD. This mini project is a two traffic light controller with a seven segment display to go with LED outputs.

    FPGA Verilog / VHDL
    £14 (Avg Bid)
    £14 Avg Bid
    2 bids
    Bid now
    EtherCAT slave implement in VHDL/Verilog. Ended

    Hello ,rnrnFor my Project, we need Data Acquisition from Sensors to DE2-115 Developmental board by FPGA implement EtherCAT slave and via an ADC.rnrnDescription:rnrnWe need to implement an over sampling ADC for an interface between Sensor and the developmental board ( DE2-115). mostly 16 bit. SPI interface is already used, so look for another one.rn There is an CODEC ( WM 8731 ) but audio already available on DE2-115, in case it useful.rnrnThen for Data acquisition, DE 2-115 board need to be implemented as EtherCAT slave, and data to be store in Dual - Port RAM, with bit rate of 40 GBPS, if possible more.rnrnIts a data acquisition project, the data from Sensors are fed to TI controller via FPGA board.rnrnlet me knw, in case of additiona...

    Electronics Embedded Software Verilog / VHDL
    £8 - £24
    £8 - £24
    0 bids
    Bid now
    vhdl Ended

    I am looking for a freelancer to help me with my project. The skills required are C Programming, C++ Programming, FPGA and Verilog / VHDL.

    C Programming C++ Programming FPGA Verilog / VHDL
    £337 (Avg Bid)
    £337 Avg Bid
    21 bids
    Bid now
    Simple calculator Verilog Ended

    My project is to design simple calculator that do this operations (+,-,/,*) and the number of decimal digits are limited to 4 . So, Enter one number (with 1 to 4 digits and could be positive or negative), enter an operator (+, - , *, /), then enter another number. At this point if “=” is entered, the answer should show. So on

    Verilog / VHDL
    £234 (Avg Bid)
    £234 Avg Bid
    23 bids
    Bid now
    Write FPGA code in Verilog for ADC data acquisition, processing and transmitting Ended

    Write code for FPGA (Lattice) in Verilog (required this specific language) for 8-bit parallel input data acquisition from ADC (8-bit ADC MAX1192), data processing (8-bit ADC data from baseband), and data sending (SPI, RS-232, etc). The 8-bit parallel data will be coming from RF base band to FPGA. It is required to sample ADC (MAX1192) at specific CLK frequency, receive data from it. During data receive specific preamble needs to be found. Data following the preamble has to be received, processed and output to SPI or serial (USB). Upon completion first part of the project (above) additional project input and support may be required (separate contract and compensation). MAX1192 datasheet:

    Programming Verilog / VHDL
    £509 (Avg Bid)
    £509 Avg Bid
    7 bids
    Bid now
    alarm clock - Repost - open to bidding Ended

    ...clock cycle in duration) the alarm should turn off and then turn back on after 5 minutes. g) Repeat snooze button simulations (pulses) should cause the same behavior in the circuit. h) If at any time the alarm set input signal goes low, the Alarm_On output should go low by the end of the next complete clock cycle. i) Clearly describe any additional rules or assumptions. Write a VHDL or Verilog code that implements the above alarm clock. Use one-hot encoding for state encoding. Verify the functionality and behavior of the circuit. Use Quartus II toolset. Submit a report containing the following: 1. A state diagram showing the implementation of your design (overview of your design, a detailed description of your approach and design process). Clearly show all the states an...

    Verilog / VHDL
    £64 (Avg Bid)
    £64 Avg Bid
    11 bids
    Bid now
    Verilog coding Ended

    Project description once we chat. Its just a lot to eplain or upload

    Verilog / VHDL
    £82 (Avg Bid)
    £82 Avg Bid
    17 bids
    Bid now
    Digital Signal Generator Ended

    i have to create digital signal generator using fpga with different voltages and different frequecies. i have the digital to analog converter pheripheral board compatible with my basys 3 development board. the dilient da2 board already give the verilog code for the module i want ur help to generate different waves forms with different voltages and frequecie

    FPGA Verilog / VHDL
    £64 (Avg Bid)
    £64 Avg Bid
    2 bids
    Bid now
    get verilog codes Ended

    c programming

    C Programming Software Development
    £94 (Avg Bid)
    £94 Avg Bid
    7 bids
    Bid now
    verilog code with testbench for face recognition (using pca) Ended

    i want a code in Verilog/vhdl for face detection finite state machine. As output, only the simulated waveforms must be displayed. Each state can be considered as one facial aspect. Include only foreheaed, eyes, nose, cheekbones, lips, chin

    FPGA Verilog / VHDL
    £41 (Avg Bid)
    £41 Avg Bid
    4 bids
    Bid now
    SystemVerilog and Verilog verification Ended

    I have a verilog code for string matcher. What i want from you is to write a verilog testbench for the design file and GUI report of it. I also want you to write a systemverliog testbench for the design file which can get the results of self checking, randomization and 100% functional analysis. If possible, documentation of this whole process is also needed.

    Verilog / VHDL
    £111 (Avg Bid)
    £111 Avg Bid
    6 bids
    Bid now
    Android 3 month full time contract (onsite) Melbourne Australia Ended

    We have a very high profile corporate client (Melbourne, Australia) looking for the following roles to start within the fortnight. · Senior Android Developer – 3 Months on-site · Other requirements: · Developers should be full stack and familiar with automation and integration into complex services. · Designer, familiar with sketch and either framer, principle or flinto. · Each should have their own hardware. This engagement is with the outlook that in the new financial year move to longer term partnership.

    Android Mobile App Development
    £27072 (Avg Bid)
    £27072 Avg Bid
    75 bids
    Bid now
    Write a Business Plan Ended

    Required 5 years Business plan with financial projections for E1 US visa.

    Business Plans
    £376 (Avg Bid)
    £376 Avg Bid
    28 bids
    Bid now
    Graph Processing Tool Ended

    Create digital signal generator using fpga with different voltages and different frequecies with digital to analog converter pheripheral board compatible with my basys 3 development board. Have Digilent da2 board verilog code for the module.

    FPGA Verilog / VHDL
    £43 (Avg Bid)
    £43 Avg Bid
    2 bids
    Bid now
    FPGA verilog3 Ended

    Looking for expert in FGPA VERILOG

    Verilog / VHDL
    £322 (Avg Bid)
    £322 Avg Bid
    13 bids
    Bid now
    Digital signal generator Ended

    Digital signal generator verilog code need to create using fpga basys 3 development board and digilent pmon DA2 board.

    FPGA Verilog / VHDL
    £40 (Avg Bid)
    £40 Avg Bid
    10 bids
    Bid now
    Picture Frame Corners Ended

    We have 52 images of picture frames that we need to have cleaned up and made into "corner samples." I've attached a sample of a source image, profile outlines + what we need. Specifically: Deliverable 1 = an image that can be used in our virtual framing software. (Image Framer 3 by Apparent Software. Free demo with good explanation of how interface works) Basically we need a small section of the frame that is straight and "loops" so that the left end of the frame meets up perfectly with the right end of the frame - thus when you put it into the software it renders well. (See ) Deliverable 2 = A virtual "corner" so that our customers can see what our frames look like. What size they are and the shape of the profile. (See ) Scale and prop...

    Graphic Design Illustration Photo Editing
    £82 (Avg Bid)
    £82 Avg Bid
    33 bids
    Bid now
    matlab project Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is £250 - £750 GBP. I have not provided a detailed description and have not uploaded any files.

    Matlab and Mathematica
    £329 (Avg Bid)
    £329 Avg Bid
    3 bids
    Bid now
    Face Recognition using Eigenfaces in FPGA Ended

    Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved face data...

    Electrical Engineering Mathematics Matlab and Mathematica
    £15 / hr (Avg Bid)
    £15 / hr Avg Bid
    9 bids
    Bid now
    Hire a VHDL/Verilog Expert Ended

    Hi, I would like to hire an expert in VHDL to help us implement an algorithm.

    Electrical Engineering Engineering FPGA Verilog / VHDL
    £115 (Avg Bid)
    £115 Avg Bid
    18 bids
    Bid now
    verilog solver Ended

    Quadratic programming

    Electrical Engineering Matlab and Mathematica Verilog / VHDL
    £14 (Avg Bid)
    £14 Avg Bid
    3 bids
    Bid now
    Quadratic programming solver - 15/03/2017 03:19 EDT - open to bidding Ended

    The project that I am looking for is quadratic programming solver in verilog/VHDL. This has lot of matrix operations. Please let me know if you will be able to get this done. Thanks, Pavan

    Electronics Embedded Software Engineering Microcontroller Verilog / VHDL
    £845 (Avg Bid)
    £845 Avg Bid
    5 bids
    Bid now
    Quadratic programming solver - open to bidding Ended

    The project that I am looking for is quadratic programming solver in verilog/VHDL. This has lot of matrix operations. Please let me know if you will be able to get this done. Thanks, Pavan

    Electronics Embedded Software Engineering Microcontroller Verilog / VHDL
    £1005 (Avg Bid)
    £1005 Avg Bid
    8 bids
    Bid now
    UVM System Verilog Expert AXI-DDR verification Ended

    Looking for UVM expert to integrate simple UVM env for AXI - DDR verification. You can use any exisitng AXI UVM library. I won't be able to provide much files except Virtual interface.. Looking for someone who can work on this during next 3-4 days and finish.

    Electrical Engineering Electronics Verilog / VHDL
    £170 (Avg Bid)
    £170 Avg Bid
    5 bids
    Bid now
    I would like to hire a Verilog / VHDL Designer Ended

    i will make a vhdl cod of aes algorithme

    Verilog / VHDL
    £159 (Avg Bid)
    £159 Avg Bid
    4 bids
    Bid now
    Script to simulate web traffic (create fake traffic) Ended

    I need a php or perl script that will simulate web traffic to a page given a set of inputs. There will be 3 sets of inputs with the following attributes in each: url, referrer, browser, p1, p2, p3, p4, p5, p6, id1, id2, id3, id4, id5, id6, cv1, cv2, cv3, cv4, cv5, cv6, e1, e2, e3, e4, e5, e6. The script will start on {url} then it will go to {p1} where it will set cookie1 with value {cv1} then it will click the element with id {id1} then it will hit an external link {e1}. Repeat for 2,3,4,5,6. The script should rotate through the 3 sets of attributes randomly until it reaches 200. DM me with any questions. I'll work with you on the requirements as long as we can achieve the same result. I prefer someone who is creative or who's done something simil...

    Perl PHP
    £12 - £20 / hr
    Featured Sealed
    £12 - £20 / hr
    12 bids
    Bid now
    develop a FPGA application Ended

    Design using Verilog, implement on Artix-7 XC7A100T-CSG324 chip, and tested within Xilinx development environment a Fast Fourier transform (FFT) algorithm. Code must be clear, well commented, and delivered with testing results. I will testing the function of the project FFT against Xilinx Vivado's build in FFT function prior to declaring project complete.

    App Design FPGA Microcontroller Verilog / VHDL
    £181 (Avg Bid)
    £181 Avg Bid
    11 bids
    Bid now
    Quadratic programming solver Ended

    The project that I am looking for is quadratic programming solver in verilog/VHDL. This has lot of matrix operations. Please let me know if you will be able to get this done. Thanks, Pavan

    Electronics Embedded Software Engineering Microcontroller Verilog / VHDL
    £785 (Avg Bid)
    £785 Avg Bid
    1 bids
    Bid now
    Quadratic programming solver - 15/03/2017 03:19 EDT Ended

    The project that I am looking for is quadratic programming solver in verilog/VHDL. This has lot of matrix operations. Please let me know if you will be able to get this done. Thanks, Pavan

    Electronics Embedded Software Engineering Microcontroller Verilog / VHDL
    £785 (Avg Bid)
    £785 Avg Bid
    1 bids
    Bid now
    verilog coding Ended

    IEEE 754 compliant floating point multipliers

    Coding Software Architecture Software Development Verilog / VHDL
    £249 (Avg Bid)
    £249 Avg Bid
    11 bids
    Bid now
    verilog coding Ended

    IEEE 754 compliant floating point multipliers

    Coding Software Architecture Software Development Verilog / VHDL
    £294 (Avg Bid)
    £294 Avg Bid
    5 bids
    Bid now
    matlab Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    Algorithm FPGA Matlab and Mathematica Verilog / VHDL
    £399 (Avg Bid)
    £399 Avg Bid
    20 bids
    Bid now
    Help me write something Ended

    I need you to write a research article. The project is based on Retiming and is to be done in verilog using xilinx software.

    Research Writing
    £45 (Avg Bid)
    £45 Avg Bid
    2 bids
    Bid now
    Write some Software Ended

    VHDL/ Verilog implementation of Image Processing Algorithms on FPGA. For 1K X 256 pixels and transfer the processed and raw bits over USB2.0 interface to Display Module. I want an experienced engineer with around 6 year or more work experience over the similar kind of projects/ development. The interested candidate can approach and other details shall be shared over email.

    Data Processing FPGA Imaging Parallel Processing Verilog / VHDL
    £106 (Avg Bid)
    £106 Avg Bid
    1 bids
    Bid now
    Project : Digital Filter using IP Block/Verilog VHDL code Ended

    I need to design a Digital filter (LPF HPF BPF BSF) by FPGA

    Matlab and Mathematica Verilog / VHDL
    £95 (Avg Bid)
    £95 Avg Bid
    16 bids
    Bid now
    Design a "Dont Fall of the Cliff" game in Verilog Ended

    Design a "Don't Fall Off the Cliff!" game: There are 3 people (represented by 3 LEDs) tied together on the top of a cliff! They are running left and right in a panic but you need to prevent them from falling off the cliff or it's game over! • At the start of the game, these three people appear on the cliff. • Pressing the middle pushbutton starts the game and these three people will run towards the left / right. • Toggling the left and right pushbuttons will change their direction and make them move towards the left or right respectively. • There are two ways to increase the difficulty of the game: (1) Reducing the width of the cliff: Changing the left cliff boundary: Use SW15 / SW14 / SW13 Changing the right cliff boundary: Use SW0 / SW1...

    Circuit Design Digital Design FPGA Verilog / VHDL
    £13 (Avg Bid)
    £13 Avg Bid
    2 bids
    Bid now
    Create a Powershell Script Ended

    ...generated the TXT file. Column E is the only column that can be empty. Note #2: Column D, must be always contain numerical values. The values -1, 0, 1 and 2 are the only values that can exist in this column. -------------------------------- CRITERIA: Let's say that in the CSV file the first row is populated as follows: A1 = UndertakerzZz B1 = TakerzZz Media C1 = C:UndertakerzZzMedias List D1 = -1 E1 = UndertakerzZz Media - Part 1 When I drag and drop the CSV to the Script... I would like the script to generate a TXT file, and inside the TXT file the first line should follow this criteria: UndertakerzZz|TakerzZz Media|<C:UndertakerzZzMedias List>|-1|UndertakerzZz Media - Part 1 Note #3: So basically the symbol "|" should separate all the fields (col...

    Powershell WordPress
    £17 (Avg Bid)
    £17 Avg Bid
    1 bids
    Bid now
    Project for simonfrfr Ended

    Hi simonfrfr, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Secure SD Memory card adapter to be used on a game console Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final device. Verilog code has: SPI interface SD slave interface AES encryption ISO7816 interface Platform is Actel/Microsemi A3P250 FPGA and development platform is A3P1500E on Microsemi A3P starter kit.

    Electrical Engineering Electronics FPGA Microcontroller PCB Layout
    £1177 - £1177
    £1177 - £1177
    0 bids
    Bid now
    Project for simonfrfr - 06/03/2017 09:40 EST Ended

    Hi simonfrfr, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Secure SD Memory card adapter to be used on a game console Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final device. Verilog code has: SPI interface SD slave interface AES encryption ISO7816 interface Platform is Actel/Microsemi A3P250 FPGA and development platform is A3P1500E on Microsemi A3P starter kit.

    Electrical Engineering Electronics FPGA Microcontroller PCB Layout
    £1177 - £1177
    £1177 - £1177
    0 bids
    Bid now
    Showing 1951 to 2000 of 2,000 entries
    Results per page