uvm env enhancement

In Progress Posted 2 years ago Paid on delivery
In Progress

enhance existing uvm environment

Verilog / VHDL

Project ID: #32590185

About the project

1 proposal Remote project Active 2 years ago

Awarded to:

raulbehl

Hello! As discussed. Happy to work along. Looking forward to our meeting. Will be happy to help you Thank you,…. Rahul…

€17 EUR / hour
(79 Reviews)
6.2