Build a LMS adaptive FIR Filter

In Progress Posted 2 years ago Paid on delivery
In Progress

Implementation of Adaptive Filter for echo cancellation using FPGA and verilog.

Verilog / VHDL Software Architecture Electrical Engineering

Project ID: #31904205

About the project

7 proposals Remote project Active 2 years ago

Awarded to:

yanatejaip5s

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution En More

$224 USD / hour
(3 Reviews)
2.8

7 freelancers are bidding on average $59/hour for this job

tangramua

Hello qth12024,   We have 20 years of strong experience in Verilog / VHDL, Software Architecture, Electrical Engineering, as a result, we can successfully complete this project.   Please, review our profile here: https More

$25 USD / hour
(21 Reviews)
6.4
BOSIREX

Am a Mechatronic engineer with 5 year experience in my field and I believe i can handle your task to perfection

$50 USD / hour
(55 Reviews)
5.5
lsjlsj04127

Hello? Let's discuss the project through chat so we can get more details and start the project soon. Waiting for you. Thank you very much.

$30 USD / hour
(1 Review)
4.8
bipinmandal736

I am a fourth-year student from the Department of Electronics and Electrical Communication Engineering. This is the domain of my interest. I shall be able to do this in a few hours. I have more than 12 months of contin More

$30 USD / hour
(21 Reviews)
4.7
manuusumer

I'm masters in ece can help you to get full implementation of project but need to discuss verilog domain if suitable

$26 USD / hour
(0 Reviews)
0.0