PSR aware CMOS Low Dropout Regulator -- 2

$250-750 SGD

Closed

Posted

over 4 years ago

$250-750 SGD

Paid on delivery

Building simulation design for CMOS low dropout regulator that can address PSR in Cadence virtuoso environment by using TSMC40nm design tools. Requirements: Familiar with software and design tools Simulation results, charts and graphs Results analysis To be complete by29august

Electrical Engineering

Electronics

Engineering

Matlab and Mathematica

Verilog / VHDL

Project ID: 20899373

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3 proposals

Remote project

Active 5 yrs ago

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3 freelancers are bidding on average $917 SGD for this job

@umg536

Hi there, please leave a message on my chat so we can discuss the budget and deadline of the project. I have read your project description and i'm confident i can do this project for you perfectly. Thanks . .

$1,500 SGD in 5 days

5.0

(28 reviews)

6.6

@mogawad

Dear client, I read about your project and I can do it for you, I'm microelectronics engineer and I used virtuoso many times throughout my projects. contact me because I've some questions and concerns to ask about.

$1,000 SGD in 8 days