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Building a HEVC Intra prediction block for FPGA

$30-250 USD

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about 8 years ago

$30-250 USD

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Designing a HEVC Intra prediction block in Verilog for a Xilinx Nexys Video FPGA board. FPGA should take a picture as input and should give encoded picture as output.

Project ID: 10126474

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Active 8 yrs ago

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3 freelancers are bidding on average $250 USD for this job

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I am an experienced VLSI engineer with strong verilog and FPGA architecture knowledge. I hope I can deliver a good result for your project.

$150 USD in 4 days

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Fresno, United States

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