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    2,000 cyclone5 fpga jobs found, pricing in GBP
    Project : Digital Filter using IP Block/Verilog VHDL code Ended

    I need to design a Digital filter (LPF HPF BPF BSF) by FPGA

    Matlab and Mathematica Verilog / VHDL
    £96 (Avg Bid)
    £96 Avg Bid
    16 bids
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    Digital filter design (FIR) using FPGA in the loop Ended

    I need help to run the project. I already have the whole project files but don't know how to run it. Just need a guidance how to run it. See the proposal attached here for more understanding of the project.

    Digital Design FPGA Matlab and Mathematica Software Testing Verilog / VHDL
    £281 (Avg Bid)
    £281 Avg Bid
    10 bids
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    Project for simonfrfr Ended

    Hi simonfrfr, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Secure SD Memory card adapter to be used on a game console Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. ...Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final device. Verilog code has: SPI interface SD slave interface AES encryption ISO7816 interface Platform is Actel/Microsemi A3P250 FPGA and development platform is A3P1500E on Microsemi A3P st...

    Electrical Engineering Electronics FPGA Microcontroller PCB Layout
    £1193 - £1193
    £1193 - £1193
    0 bids
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    Project for simonfrfr - 06/03/2017 09:40 EST Ended

    Hi simonfrfr, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Secure SD Memory card adapter to be used on a game console Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. ...Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final device. Verilog code has: SPI interface SD slave interface AES encryption ISO7816 interface Platform is Actel/Microsemi A3P250 FPGA and development platform is A3P1500E on Microsemi A3P st...

    Electrical Engineering Electronics FPGA Microcontroller PCB Layout
    £1193 - £1193
    £1193 - £1193
    0 bids
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    Secure SD card reader Ended

    Secure SD Memory card adapter Review verilog code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final dev...code, optimize code size and debug on hardware development kit. Code an IS07816 secure mcu interface and test all verilog operations. Add a handshake with Software for transfer of MAC Address Debug and optimize where needed. Compile for and test for final device. Verilog code has: SPI interface SD slave interface AES encryption ISO7816 interface Platform is Actel/Microsemi A3P250 FPGA and development platform is A3P1500E on Microsemi A3P starter kit. ...

    Electrical Engineering FPGA Verilog / VHDL
    £938 (Avg Bid)
    £938 Avg Bid
    10 bids
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    Implementation of ADSB (Automatic dependent survillance broadcast) using zedboard and AD9361 Ended

    I/Q Interface to analog device AD9361 for the ADS-B RF Interface (1090 MHz with 8Msps) the existing algorithms on the Zync FPGA. The Algorithms are the decoding of the ADS-B signal which is PWM based. the Algorithm to SW (Dual ARM) and HW (FPGA)

    Matlab and Mathematica Python
    £268 (Avg Bid)
    £268 Avg Bid
    1 bids
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    CMOS sensor FPGA interfacing Ended

    CMOS sensor interfacing with Cyclon III FPGA . to do high speed image acquisition. Implement DDR2 based memory grabbing with FPGA CMOS senor interfce with FPGA with 400 MBPS speed SPI interface in FGPA Werite VHDL code for the above.

    Software Architecture
    £441 (Avg Bid)
    £441 Avg Bid
    1 bids
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    vhdl expert need with board Ended

    The board I use (Basys 3 Artix-7 FPGA).writing program by Vivado - Xilinx VHDL and some part with assembly attached doc is the task In this attachment you find many files inside. first one call it assignment 2 this I tried to write some code and added many files maybe help you in your work. also you find two files PDF first one call "Lec_Microprocessor_Design" inside this file you can see final design for the assignment that in page divided many part you can see,(ALU,register, memory, control unit and .....) Next in ALU you need making many job 1. Addition 2. Subtraction 3. Increment A 4. Decrement A 5. LT - Less Than 6. Not A 7. Logic AND 8. Logic OR Finally in this attachment also you find three videos First one about how addition work second one...

    Digital Design Electrical Engineering Electronics FPGA Verilog / VHDL
    £68 (Avg Bid)
    £68 Avg Bid
    5 bids
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    fpga design Ended

    Create an image processing application (image halftoning) on DE1-SOC board and display it on VGA monitor.

    FPGA Matlab and Mathematica Verilog / VHDL
    £135 (Avg Bid)
    £135 Avg Bid
    7 bids
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    FPGA + eMMC interface Development Ended

    I'm looking for freelancer who is able to develop the FPGA + eMMC memory

    FPGA Verilog / VHDL
    £4214 (Avg Bid)
    £4214 Avg Bid
    4 bids
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    EE2020 digital electronics FPGA verilog - open to bidding Ended

    improve my verilog fundamentals and help with verilog fpga project.. still learning how to program the leds and push buttons

    Circuit Design Digital Design Electrical Engineering Electronics Verilog / VHDL
    £21 / hr (Avg Bid)
    £21 / hr Avg Bid
    15 bids
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    perform halftoning operation on image, on de1 soc board - open to bidding Ended

    Ultimate goal of my project is to make an application on image processing on DE1 Soc, which shows the communication between HPS and FPGA , but first i have to start with the halftoning operation on image and to load that image on de1-soc board.

    Electronics FPGA Matlab and Mathematica Microcontroller Verilog / VHDL
    £317 (Avg Bid)
    £317 Avg Bid
    5 bids
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    Sr Go Developer with Distributed Systems Ended

    Sr Go Developer with Distributed Systems and Blockchain experience to develop backend for Blockchain database powered by Tendermint () for Vulcanize, Inc. (http://vulcan...() for Vulcanize, Inc. () Vulcanize is a technology company focused on blockchain database development. * Multinode - distributed network protocols such as IP routing, BGP, Cellular, or WiFi * Multi-core/Multi-thread - multiple processes concurrently working on shared data * Coprocessing - the acceleration of a system via an FPGA, GPU, DSP, vector unit or other co-processor * Advanced data structures and algorithms. RCU (read-copy-update), DHT (distributed hash tables), Blockchains, Graphs/Networks, etc.

    Bitcoin C# Programming C++ Programming Golang Software Architecture
    £29 / hr (Avg Bid)
    £29 / hr Avg Bid
    9 bids
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    EE2020 digital electronics FPGA verilog Ended

    improve my verilog fundamentals and help with verilog fpga project.. still learning how to program the leds and push buttons

    Circuit Design Digital Design Electrical Engineering Electronics Verilog / VHDL
    £27 / hr (Avg Bid)
    £27 / hr Avg Bid
    1 bids
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    perform halftoning operation on image, on de1 soc board Ended

    Ultimate goal of my project is to make an application on image processing on DE1 Soc, which shows the communication between HPS and FPGA , but first i have to start with the halftoning operation on image and to load that image on de1-soc board.

    Electronics FPGA Matlab and Mathematica Microcontroller Verilog / VHDL
    £199 (Avg Bid)
    £199 Avg Bid
    1 bids
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    I have to work on De1 SOC board and create an application on image processing which can use both hps and fpga. Ended

    I have to work on DE1-SOC board and create an application on image processing which can use both HPS and FPGA . but at first I have to perform the halftoning operation on an image.

    Verilog / VHDL
    £662 (Avg Bid)
    Urgent
    £662 Avg Bid
    2 bids
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    VHDL expert with board Ended

    I can send all the details upon request.. looking for VHDL expert to handle a task sign meets the specifications; d) report about your design. You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx Artix 7 FPGA) in order to implement a design that meets the specifications (below). You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of nonstandard packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSI...

    Electronics FPGA Verilog / VHDL
    £24 (Avg Bid)
    £24 Avg Bid
    8 bids
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    Searching LinkedIn for individuals with specific skills and criteria for a business, and providing all of the necessary information. Ended

    Looking to fill the two following roles with the attached skill-sets: 1. C++ Developer – Algorithmic Trading Systems · C++, LINUX, · Latency, · High Frequency, · HFT, · parallel programming, · MPI, · CUDA, · GPU, · FPGA, · network programming, · sockets, · trading system 2. Head of Quantitative Trading Research · 5 - 10 years experience · Based in NYC (currently or formerly) · High frequency trading · Quantitative execution · Alpha generation · Futures, Cash Treasuries &mi...

    Linkedin Research
    £107 (Avg Bid)
    NDA
    £107 Avg Bid
    13 bids
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    Design me a Product FPGA Ended

    my project is trucking multi color based broad DE1-SoC i using camera D8M-GPIO my code write VHDL is already just i need modify to racking multi color i try many time i hope any one can solve my problem thanks

    Product Design
    £33 (Avg Bid)
    £33 Avg Bid
    1 bids
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    FPGA implementation of SVM Ended

    I need a freelancer do do a FPGA implementation of SVM

    Electrical Engineering
    £107 (Avg Bid)
    £107 Avg Bid
    5 bids
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    Write a Technical Report ( FPGA & VHDL ) -- 2 Ended

    Need who can solve technical issue related to : Keywords : Implementing a 2-D FFT on FPGA , desgining , ADC , FPGA chip, (FIFO , FFT , pipelined streaming I/O architecture, FFT alghorithm , Vivado , Verilog , VHDL , FPGA chip is Artix-7 , budget= 60$ deadline 6 days

    Electrical Engineering Electronics FPGA Verilog / VHDL Wireless
    £115 (Avg Bid)
    £115 Avg Bid
    7 bids
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    FPGA VERILOG 1 Ended

    LOOKING FOR EXPERT IN VERILOG FOR ADVANCED PROJECT

    Verilog / VHDL
    £434 (Avg Bid)
    £434 Avg Bid
    20 bids
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    Write a Technical Report ( FPGA & VHDL ) Ended

    Need who can solve technical issue related to : Keywords : Implementing a 2-D FFT on FPGA , desgining , ADC , FPGA chip, (FIFO , FFT , pipelined streaming I/O architecture, FFT alghorithm , Vivado , Verilog , VHDL , FPGA chip is Artix-7 , budget= 60$ deadline 6 days

    Electrical Engineering Electronics FPGA Technical Writing Telecommunications Engineering
    £111 (Avg Bid)
    £111 Avg Bid
    11 bids
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    electronic design orcad Ended

    I need an expert of electronic schematic entry, and especially ORCAD, for capturing an electronic schema. I have the paper version with a similar design and need to transform in electronic format using ORCAD. The schema is based on XILINX ZYNQ FPGA and DDR memories, and power supply.

    CAD/CAM Electrical Engineering Electronics PCB Layout
    £591 (Avg Bid)
    £591 Avg Bid
    3 bids
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    FPGA code Ended

    Write code to do HD video compression and decompression on a Altera Cyclone V SoC. Use VHDL in FPGA OR use ARM processor with LINUX, OpenCL. Compressed video must be saved and read to/from SD-card

    FPGA Microcontroller Software Architecture Software Development Verilog / VHDL
    £880 (Avg Bid)
    £880 Avg Bid
    6 bids
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    design VHDL based temperature controller Ended

    - To design the VHDL based temperature controller that comprises of SPI controller, Data converter, Memory block and Display drivers. - To develop the test bench to test the design for both behavioral and timing model using Modelsim. -Implement the design in FPGA and accomplish the hardware testing.

    FPGA Verilog / VHDL
    £161 (Avg Bid)
    £161 Avg Bid
    9 bids
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    design the VHDL based temperature controller Ended

    - To design the VHDL based temperature controller that comprises of SPI controller, Data converter, Memory block and Display drivers. - To develop the test bench to test the design for both behavioral and timing model using Modelsim. - Implement the design in FPGA and accomplish the hardware testing. (optional)

    FPGA Verilog / VHDL
    £8 - £24
    £8 - £24
    0 bids
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    6522 VIA FPGA Emulation Ended

    This project consists of emulating a 6522 VIA on an FPGA. The 6522 VIA is part of a legacy Sound Card. So I have a working design in which to test the emulation. See the attached schematic file for how the 6522 (U3) is connected, and which pins are used. I am currently using a GODIL FPGA module to connect to the Sound Card. This consists of a Xilinx Spartan 3E 500 Gate FPGA. Attached is also the project files I have been using for testing. I found an Open Source core () and based the project on that. However I am getting very inconstant results when writing and reading to the FPGA using a test program. When I replace the FPGA with a DIP 6522 the tests pass 100% and the Sound Card works 100%. See attached files for 6522

    Electronics FPGA Verilog / VHDL
    £168 (Avg Bid)
    £168 Avg Bid
    2 bids
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    Write some Software Ended

    8 bit microcontroller design and implementation in FPGA with spartan 3

    Verilog / VHDL
    £235 (Avg Bid)
    £235 Avg Bid
    9 bids
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    Project for vinodluhar Ended

    Capture a Depth image in Kinect v1 and apply smoothing filter using FPGA (Zedboard). Example filter:

    Electronics FPGA LabVIEW PCB Layout Verilog / VHDL
    £40 - £40
    £40 - £40
    0 bids
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    Hire an Engineer Ended

    Hardware should be finalized in a month, price negotiable. Hi, I'm Sherman and I am a full-stack web developer. The product I am...processes it and outputs a Boolean(yes/no). The code is available for processing the specific technology. The current MVP is done with an Audrino board but we are open to switching the board as long as it fulfills its function. The MVP was coded in python but we have no language preference for the prototype. The engineer should knowledge/skills in the following areas: - Consumer Electronics - FPGA Boards - Embedded system - IoT experience (preffered, not required) We do not require a specific education background but we do have to see some of the past projects that you have worked on. We are serious about the pursuit, do reach out to us f...

    Electrical Engineering Electronics Engineering
    £2049 (Avg Bid)
    £2049 Avg Bid
    5 bids
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    FPGA VERILOG Ended

    Looking for expert in verilog to fix program or code from scratch

    C Programming C++ Programming Verilog / VHDL
    £345 (Avg Bid)
    £345 Avg Bid
    14 bids
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    FFT in Hardware based on an FPGA implementation Ended

    Implement FFT in FPGA based on 256 samples. Each sample has 16bit real and 16bit imaginary. The tool is called LiberoSoC from Microsemi and FPGA is smart fusion 2 igloo.

    Electronics FPGA Shell Script Verilog / VHDL
    £195 (Avg Bid)
    £195 Avg Bid
    9 bids
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    Write some software -- 7 Ended

    I need you to develop some software for me. I would like this software to be developed using C or C++.FPGA PROGRAMMING USING VERILOG TO DESIGHN ALGORITHM ASK ME FOR DETAILS. MINIMUM EXPERIENCE 3 YEARS NOT FOR LEARNERS.

    C Programming C++ Programming Software Architecture
    £391 (Avg Bid)
    £391 Avg Bid
    13 bids
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    Develop FPGA code Ended

    We want to implement some functions on FPGA boards like Xula, Zedboard, etc. - Freelancer should be able to assist our team in achieving its goals by developing and testing the modules/functions.

    C Programming Python Verilog / VHDL
    £207 (Avg Bid)
    £207 Avg Bid
    8 bids
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    VERILOG DESIGN OF ALGORITHM ON FPGA Ended

    VERILOG EXPERT AT LEAST 3 YEARS WORK EXPERIENCE TO FIX CODE OR DESIGN FROM SCRATCH ALGORITHM

    C Programming C++ Programming
    £118 (Avg Bid)
    £118 Avg Bid
    11 bids
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    fpga Ended

    image enhancement algorith must be implemented on a fpga

    Arduino FPGA LabVIEW Microcontroller Verilog / VHDL
    £466 (Avg Bid)
    £466 Avg Bid
    20 bids
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    Medical Laser Ended

    Embedded device - module finalization & system integration (project modules already 75% complete) Altera SoC DE1 (Dual ARM HPS & Cyclone FPGA) QT HMI Linux on ARM Quartus II for Cyclone NIOS soft processors on FPGA

    C Programming Embedded Software FPGA Linux
    £3015 (Avg Bid)
    £3015 Avg Bid
    7 bids
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    Write some Software Ended

    Micro controller design and implementation in FPGA.

    Verilog / VHDL
    £93 (Avg Bid)
    £93 Avg Bid
    8 bids
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    General Help in FPGA design - Need someone from Israel only. You will need to be in our office Ended

    We need a 4-6 month help with our project. Verilog is a must. VHDL is nice to have. FPGA Xilinx experience is an advantage

    FPGA Verilog / VHDL
    £6626 (Avg Bid)
    £6626 Avg Bid
    1 bids
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    General Help in FPGA design Ended

    We need a 4-6 month help with our project. Verilog is a must. VHDL is nice to have. FPGA Xilinx experience is an advantage

    FPGA Verilog / VHDL
    £6019 (Avg Bid)
    £6019 Avg Bid
    8 bids
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    Design and implementation of a 24-hour digital clock on Xilinx FPGA Using VHLD Method Ended

    Counter A counts from 0 to 9. When it reaches to 9, on the next clock, Counter B increments by 1 (i.e. Q3Q2Q1Q0 = 0001) Counter A repeats counting and again when it reaches to 9, Counter B increments to 2 (i.e. Q3Q2Q1Q0 = 0010). The time now shows 20 hours. Counter A starts counting again: 0000, 0001, 0010, 0011. The time is now 23 hours. on the next Count (i.e. 0100), Q2 becomes 1, Q1 of Counter B is already at 1 and therefore the AND gate generates a ‘1’ at its output which is used to reset both counters to 0000. Note that Counter B doesn’t have to be a 0 to 9 (Decade) counter as it only counts: 1and 2 but remember you need a 4-bit presentation of 1 and 2 (for the BCD to Seven Segment block). So you could have a 0 to 3 counter (requires only 2 flip flops) to ge...

    Digital Design Electronics
    £118 (Avg Bid)
    £118 Avg Bid
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    DVB-S2 Modulator on FPGA Ended

    We are planning to develope DVB-S2X modulator and we would like to work with people with experience in this field.

    Electronics FPGA Verilog / VHDL
    £11994 (Avg Bid)
    £11994 Avg Bid
    4 bids
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    fpga Ended

    Arduino FPGA LabVIEW Microcontroller Verilog / VHDL
    £371 (Avg Bid)
    £371 Avg Bid
    18 bids
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    encoder Ended

    I am looking for a freelancer to help me with my project. The skills required are CUDA, FPGA, Kinect, LabVIEW and Microcontroller. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    CUDA FPGA Kinect LabVIEW Microcontroller
    £413 (Avg Bid)
    £413 Avg Bid
    11 bids
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    Project for ducdctoandh Ended

    Hello, I need a program in FPGA (in Xilinx) able to display RGB and Microsoft Kinect Depth cameras on the VGA output of the Zedboard.

    Electronics Embedded Software FPGA Technical Writing Verilog / VHDL
    £119 (Avg Bid)
    £119 Avg Bid
    1 bids
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    Fpga in quartus Ended

    I need you to develop some software in altera quartus for cyclone IV fgpa

    Software Architecture Verilog / VHDL Windows Desktop
    £809 (Avg Bid)
    £809 Avg Bid
    11 bids
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    data encoder Ended

    I am looking for a freelancer to help me with my project. The skills required are CUDA, FPGA, Kinect, LabVIEW and Microcontroller. I am happy to pay a fixed priced and my budget is ₱10000 - ₱30000 PHP. I have not provided a detailed description and have not uploaded any files.

    CUDA FPGA Kinect LabVIEW Microcontroller
    £135 - £405
    £135 - £405
    0 bids
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    Arduino library Ended

    I am looking for a freelancer to help me with my project. The skills required are Arduino, Bluetooth Low Energy (BLE), Circuit Design, FPGA and Microcontroller. I am happy to pay a fixed priced and my budget is $125000 - $375000 CLP. I have not provided a detailed description and have not uploaded any files.

    Arduino Bluetooth Low Energy (BLE) Circuit Design FPGA Microcontroller
    £221 (Avg Bid)
    £221 Avg Bid
    20 bids
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    matlab expert need urgently Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, LabVIEW, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

    Algorithm FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
    £142 (Avg Bid)
    £142 Avg Bid
    9 bids
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