Digital logic Vivado simulation expert needed
$10-30 USD
Paid on delivery
Hi,
I have project in which I required the following parts to solve,
1) a state diagram for modeling the system as an FSM (finite-state-machine). Specify in the Sketch same sketch the meaning of each state, the input(s) and output(s).
2) Design the FSM using Verilog code and simulate the FSM. (Use comments to indicate the meaning of each variable.)
3) Write a report to explain in detail the state diagram, FSM design source code, and simulation result. Summarize the project in the report
Furthermore, you have to use simulation on vivado for this project.
Do you able to do this please see the attachment?
Project ID: #24796677
About the project
6 freelancers are bidding on average $40 for this job
Greetings to the team. We have seen your requirement is that you need to implement the specified scenario in verilog FSM with state diagram and a report for the same. We are expert in this implementation. So I can More
i have 2+ year experience in design and verification, i have done 25+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support after completion of project, thanks and regard More
hi, I will work on this in a day and will be ready with VIVADO simulations for your target technology in no time. I have experience in both FSM design and Verilog since its the only two works I do.
I am an Electronics Engineer. I have experience with xlinx fpga verilog programing. I am confident i can deliver you this project. If you like you can discuss any ambiguity in chat.
