RTL Design Engineer (3 years):
* RTL Design Ownership:
- Distributed System/L3 Cache
- ACE/ACE-L/AXI slave ports for North Bridge
- Distributed Register file
- Routing blocks for North Bridge
* Generation of North Bridge top-level and Multi Chip Topologies using Synopsys GenSys
* Simulation and emulation debugging
* Verification of North Bridge unit level (direct tests coding - UVM, coverage analysis)
Validation and FPGA Engineer (8 years):
2008 – 2016
* ASIC - Logic Validation, functional tests definition and coding (C, C++), low level drivers development (C, C++, Assembly), hand on with hardware:
- SD/MMC, SPI, NOR, UART, xMII, Packet Processor, Ethernet Switch, Ethernet MAC (full responsibility)
- DRAM, PCIe, USB, Power Management (partial responsibility)
* FPGA Development
* RTL design - Verilog coding, implementing various bridges, communication modules, protocol exercisers, lab and debug tools
* ASIC prototyping
* Static Timing Analysis
* Board Design