• Experience in FPGA prototyping of multi-million gate ASICs using Xilinx-Virtex-7, ,Zed, Spartan6, Spartan3
• Understanding of Power Management ( voltage domain, power domains, clock domains )
ASIC RTL to GDS2 ,Analog layout
• Exposure to Simulators (ncsim )
• Verilog/RTL/Conformal Verification( LEC)
• Exposure to shell, TCL.
• PCB design for multi-layer, complex boards (up to 6 layers).
• Independently handle the execution and delivery of a medium to complex blocks RTL2GDS implementation
• Developed specifications for specific FPGA designs and assisted in parsing the work between FPGA designers.
• Designed, developed wireless communications FPGA code for existing client products.
• Provided development support for wireless communications FPGA for new client products as needed.
• Adhered to the guidelines for code development as practiced by the engineering team.
• International Client Exposure