VLSI project

Closed Posted 2 years ago Paid on delivery
Closed Paid on delivery

about comparison of CMOS, pseudo NMOS and transmission gate logic in term of power delay area

Verilog / VHDL Electrical Engineering Engineering Circuit Design Electronics

Project ID: #29871060

About the project

3 proposals Remote project Active 2 years ago

3 freelancers are bidding on average $103 for this job

Itblast

Hi, this is Imran Khan Khoso. I am an Electrical Engineer with 2-4 years of experience. I can help you in: 1: CMOS Processing steps 2: Crystal Growth steps and techniques 3: Diffusion 4: Oxidation 5: Lithography More

$30 USD in 5 days
(2 Reviews)
3.2
BELMAJDOUB

Dear Sir or Madam I'm interested in your project and I can do it with the perfect method and time. I'm an expert in the design and development of analog, RF and digital integrated circuits using Cadence virtuoso, caden More

$140 USD in 5 days
(1 Review)
2.2
msgtohemanth

Experienced VLSI professional with strong knowledge in Digital design and testing. Good knowledge on various EDA tools can help you to solve it.

$140 USD in 7 days
(0 Reviews)
0.0