VLSI project
$30-250 USD
Paid on delivery
about comparison of CMOS, pseudo NMOS and transmission gate logic in term of power delay area
Project ID: #29871060
About the project
3 freelancers are bidding on average $103 for this job
Dear Sir or Madam I'm interested in your project and I can do it with the perfect method and time. I'm an expert in the design and development of analog, RF and digital integrated circuits using Cadence virtuoso, caden More
Experienced VLSI professional with strong knowledge in Digital design and testing. Good knowledge on various EDA tools can help you to solve it.