Mirror unit receives data stream via Avalon ST interface which is buffered and processed if necessary. Each steam starts with Control packet which contains description about the image like interlacing, width and height or definition of the data received (Altera's VIP has it's own protocol, it is assumed that you familiar with it).
Please read attached document for more detailed description.
Only experienced designers with proven record and positive feadback.
I am very suitable for this job because:
- Worked with Altera
- Understand the your specfication
- Familar with VHDL/FPGA
IMPORTANT: 100% JOB COMPLETED!
Relevant Skills and Experience
FPGA/VHDL/Verilog
Testing skill (testbench)
Proposed Milestones
$333 USD - the whole work