Find Jobs
Hire Freelancers

Design block in VHDL

$250-750 USD

Closed
Posted over 6 years ago

$250-750 USD

Paid on delivery
Mirror unit receives data stream via Avalon ST interface which is buffered and processed if necessary. Each steam starts with Control packet which contains description about the image like interlacing, width and height or definition of the data received (Altera's VIP has it's own protocol, it is assumed that you familiar with it). Please read attached document for more detailed description. Only experienced designers with proven record and positive feadback.
Project ID: 14736654

About the project

2 proposals
Remote project
Active 7 yrs ago

Looking to make some money?

Benefits of bidding on Freelancer

Set your budget and timeframe
Get paid for your work
Outline your proposal
It's free to sign up and bid on jobs
2 freelancers are bidding on average $528 USD for this job
User Avatar
I am very suitable for this job because: - Worked with Altera - Understand the your specfication - Familar with VHDL/FPGA IMPORTANT: 100% JOB COMPLETED! Relevant Skills and Experience FPGA/VHDL/Verilog Testing skill (testbench) Proposed Milestones $333 USD - the whole work
$333 USD in 5 days
4.9 (73 reviews)
6.1
6.1

About the client

Flag of ISRAEL
Haifa, Israel
4.7
24
Payment method verified
Member since Nov 29, 2010

Client Verification

Thanks! We’ve emailed you a link to claim your free credit.
Something went wrong while sending your email. Please try again.
Registered Users Total Jobs Posted
Freelancer ® is a registered Trademark of Freelancer Technology Pty Limited (ACN 142 189 759)
Copyright © 2024 Freelancer Technology Pty Limited (ACN 142 189 759)
Loading preview
Permission granted for Geolocation.
Your login session has expired and you have been logged out. Please log in again.