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Convert Verilog to System verilog and add UVM

₹1500-12500 INR

Closed
Posted almost 3 years ago

₹1500-12500 INR

Paid on delivery
I have working verilog modules, need to convert to system verilog module and add UVM for test bench
Project ID: 30621240

About the project

5 proposals
Remote project
Active 3 yrs ago

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5 freelancers are bidding on average ₹10,122 INR for this job
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Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and others. Please contact me to discuss more about this project. Kindest regards.
₹15,000 INR in 7 days
5.0 (18 reviews)
4.2
4.2
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i have 2.5+ year experience in design and verification, I have done 5+ bigger projects in sv/uvm i have done 30+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support after completion of project, thanks and regard kundan vaghela
₹5,000 INR in 7 days
4.9 (11 reviews)
3.5
3.5
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To Develop Testbenches for HDLs you need a good understanding of Design and HDL Modules used to extract test cases and cover each test stimulus.. VHDL, Verilog, or System Verilog ? For all of this, I Am Your Person. I have A Lot OfEexperience in exactly this Field! Your work will be finished well in time and I can add in your inputs also, if you like!
₹12,500 INR in 7 days
0.0 (0 reviews)
0.0
0.0
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Hi there, we are experts in building SV/UVM based TB. also wondering reason for changing verilog based dut to SV. please ping me to understand your requirement more
₹11,111 INR in 5 days
0.0 (0 reviews)
0.0
0.0
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Hi, I am Anjana B, trained engineer in VLSI front-end with good hands-on experience in Verilog, System-Verilog and UVM.I think my skillsets match your requirements. Looking forward to getting connected. Regards Anjana B
₹7,000 INR in 7 days
0.0 (0 reviews)
0.0
0.0

About the client

Flag of INDIA
Kolar, India
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Member since Nov 28, 2018

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