I'm a trader and I need an HPGA engineer foran ultra low latency fpga solution to trade on CME.
I have a c++ reference implementation for most blocks, obviously this needs to be converted to hdL (verilog ideally).
Functional requirements:
- Msrket Data feed handler
- Order book building (Last bid, ask, trade)
- Line arbitration (Feed A and B arbitration)
- orders sending
- Exchange orders report processing
Provided blocks (C++)
- Market data feed handler
- Order book
- orders sending
Provide fpga IPs:
- TCP/IP
- 10 GbE MAC/PCS
Hi there,I'm biddin on your project "CME HFT FPGA tick to trade -- 2"
I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the project.
Thanks.
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