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Pipelining a RISC-V processor

$50-150 USD

Completed
Posted about 3 years ago

$50-150 USD

Paid on delivery
this project is Profiling a Pipelined RV32I Implementation. needs to do some change to [login to view URL] and [login to view URL] and acchive the best effort pipeline implementation on [login to view URL] and make sure total Clock Cycles from the execute stage is less than 70,000. It should achieve the highest possible wall-clock speed, taking the clock speed into account. It will be evaluated using a vanilla rv32i implementation, without the Mul instruction. and a report addressing the questions listed in the file attached.
Project ID: 29478906

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1 proposal
Remote project
Active 3 yrs ago

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I'm computer engineer and lecturer with more than 15 years of expertise. I'm professional with Computer architecture , designing the datapath with pipleining for AVR , MIPS , and RISC -V. I'm also professional with bluespec RISC-V explorer under Ubuntu. I'm experienced with pipelining concepts such as forwarding , stalls , hardware units redundency , IPC etc. will help you with complete documentations and updating of the given .bsv files , benchmarking and fully detailed reporting.
$140 USD in 4 days
5.0 (1 review)
2.3
2.3

About the client

Flag of UNITED STATES
Irvine, United States
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Member since Mar 5, 2021

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