Cache memory - processor - cache-mapping scheme - Computer Organization and Assembly Language C++

See attached document Submit typed hardcopy as instructed. No extension will be granted. 1. [20 marks] We investigate the increase in CPI (clocks per instruction) due to cache misses that occur during memory references. For simplicity, we pretend that instruction fetches never miss. a) [10 marks] Suppose the processor takes an average of 1.5 clock cycles to execute an instruction when there are no cache misses. Assume that the miss penalty is 8 cycles and that there is an average of 1 memory reference per 3 instructions. This _base_ CPI of 1.5 cycles includes the cache hit time. Suppose the miss rate is 5%. Using the formula t_ave = ht + mr * mp, what is the CPI when cache misses are taken into account? <average time = hit time + miss rate * miss penalty> b) [10 marks] Consider the same processor with a two-level cache. The hit rates for the L1$ and the L2$ are 95% and 80%, respectively. The _local_ miss penalties are 8 cycles and 60 cycles, respectively. Assume the same density of memory references. If the CPI is 1.5 cycles when there are no cache misses, what is the CPI when cache misses are taken into account? Hint: Apply the formula recursively to find the effective miss penalty of the L1$. 2. [24 marks] 1) _Compulsory_ misses occur the first time a program touches a cache line. 2) _Conflict_ misses occur when more than 'm' lines map to the same set in an m-way set-associative cache. 3) _Capacity_ misses occur when a program's working set exceeds the cache capacity. It is hard to do much about compulsory misses, but both conflict and capacity misses are affected by the geometry parameters of a cache: its capacity, its associativity (wayness), and its cache-line size. a) [8 marks] If we increase the capacity 'S' of the cache, but keep the other two parameters constant, will i) conflict misses, and ii) capacity misses, increase or decrease? Explain. Also, is there a downside to larger caches? Explain. b) [8 marks] If we increase the associativity (wayness) 'm' of the cache, but keep the other two parameters constant, will i) conflict misses, and ii) capacity misses, increase or decrease? Explain. Also, is there a downside to increased associativity? Explain. c) [8 marks] If we increase the cache-line size 'L' of the cache, but keep the other two parameters constant, will the miss rate increase or decrease i) for programs with a high spatial locality, and ii) for programs with low spatial locality? Explain. 3. [21 marks] Consider a computer with a byte-addressable memory. A 40-bit memory address is divided as follows for cache processing. First, the 8 low-order bits are chopped off to expose the cache-line number. Second, the next 17 low-order bits are inspected to get the cache-container index. Third, the remaining 15 bits are used as the cache tag. Hint: What do the direct-mapped and set-associative placement formulas have in common? a) [7 marks] What is the cache size in bytes? b) [7 marks] What is the cache-mapping scheme? c) [7 marks] For a given byte in the cache, how many different bytes in the main memory could possibly be mapped to it? 4. [19 marks] Consider a computer with 32-bit registers. The memory is word addressed. There is a direct-mapped cache with 4K cache frames. Cache lines are 16 words. Into which cache frame, and with what tag value, does 32-bit word address '45677cba' go? Show your work. Answers in hexadecimal. 5. [16 marks] Consider a word-addressed computer whose memory latency is 200 cycles. The hardware bandwidth is 1 word/cycle. The processor manages to sustain 180 outstanding (load) memory references in each and every cycle. +2 more questions...