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JNI with OpenCL for CPU-FPGA communication

€30-250 EUR

Closed
Posted over 3 years ago

€30-250 EUR

Paid on delivery
Following this tutorial of FPGA acceleration through Vitis platform: [login to view URL] The Host Program is written by C/C++. The Kernel Program is written by C/C++. OpenCL API is the bridge to connect the Host Program and Kernel Program under Vitis execution environment. Now, while keeping the Kernel Program (C/C++) of the tutorial, I want to rewrite the Host Program by using Java code. Objective: The Java Host Program must connect successfully with the Kernel Program as the example of tutorial. To be clear, the Java Host Program could use Java Native Interface (JNI) to integrate the native code of OpenCL.
Project ID: 27454579

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1 proposal
Remote project
Active 3 yrs ago

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1 freelancer is bidding on average €250 EUR for this job
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Hi I'm an Embedded hardware / firmware design engineer with 18 years experience: • Designing Industrial motor control and speed Drive • digital Power supply design for commercial and industrial sector • digital Power Controllers TMS320F28xx series. • micro-controller programming with ARM-Cortex M4/7/33, Cortex-R, Cortex-A7/A9 / Risc-V , MIPS32 ,STM32 • IoT : BLE, Zigbee, LoRaWan, sigfox, wifi, nRF52 , CC26xx, ESP32 • Real-Time Operating systems [SafeRTOS / FreeRTOS / QNX / Mbed] • track record PCB design using Cadence Allegro / Kicad / Altium • system design and components selection and interfaces • PCB Signal integrity and Power/Thermal analysis • PCB manufacturing DFM, DFT, DFA so I invite you to chat and exchange more details about your project and show you how my experience fits your project.
€250 EUR in 7 days
5.0 (4 reviews)
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Dinan, France
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Member since Sep 21, 2020

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