Design an ALU Using Verilog -- 2
$30-250 USD
Paid on delivery
Top cell : alu
I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow
TOP MODULE: 16-bit Adder Module
PRIMARY SIGNALS: BUS inputs/outputs and additional signals
BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS:
A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0]
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Project ID: #32336677
About the project
15 freelancers are bidding on average $121 for this job
Hi I have the experience in digital circuit design for arithmetic, memory and datapath modules. I have understood your demand to design the ALU associated adder module. I can design the ALU as per your requirement. ple More
I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module with Verilog such as Convolution En More
Hi, hope you are doing good. Its hamza, an electrical engineer with a vast experience in verilog,VHDL & system verilog & have a strong knowledge of software like vivado, xilinx-ise, Quartus-ii/prime, modelsim etc. I ha More
Hi, I am an electronics engineer and have prior experience in designing an ALU using verilog. You can check my LinkedIn profile to see that I am employed on a major semiconductor company and thus have great knowledge o More
I understand what you are requiring, You are requiring an ALU for adding and having a few functions more. I will write the verilog on xilinx for FPGA And simulate the results on xilinx vivado. I can sent you sample wor More
Hello, I am an electronics student in 7th Semester and studying Verilog HDL. I am practicing Verilog programs in Model Sim. I can help you in this can we chat more in detail... Regards, Hamza
Hi, I can design/simulate/FPGA_Implement the ALU as per your requirement with my deep design experience. Please provide more details. Thanks
I have many experiences on Verilog code development for digital signal processing, high speed parallel processing and their simulations.
Hi. I designed a 32 bit RISC-V processor with Verilog this year. It was 5 stage pipelined and all hazards were handled . I used carry look ahead topology for adder. I can easily design your ALU according to adder topo More
I have three years of experience in verilog. My experience as a TA in digital systems design makes me suitable for thus job.
i have trained on vlsi and and verilog code so i can complete this module.I can deliver the code with accuracy