Xilinx DDR3 controllers development for Frame buffer (one frame delay)

$1500-3000 USD

Closed

Posted

about 6 years ago

$1500-3000 USD

Paid on delivery

• Target DDR3 controllers development for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document

Electrical Engineering

Project ID: 16415806

About the project

6 proposals

Remote project

Active 6 yrs ago

Looking to make some money?

Email address

Benefits of bidding on Freelancer

Set your budget and timeframe

Get paid for your work

Outline your proposal

It's free to sign up and bid on jobs

6 freelancers are bidding on average $2,185 USD for this job

@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using fpga please check my profile also please message me so that we can discuss best regards

$2,111 USD in 15 days

5.0

(325 reviews)

7.7

@edison4mobile

Flag of LAO PEOPLE'S DEMOCRATIC REPUBLIC

Hello how are you? I am very interested on your project. I have rich experienced in electronic engineering. In the previous, I have made altera circuit. In that circuit, there are FGPA, CYCLONE, DDR2, RAM, ROM. Also I have made all firmware and signal processing program including driver and desktop application. If you hire me, I will do my best and can deliver high quality project to you. Thanks a lot.

$2,500 USD in 30 days

5.0

(3 reviews)

3.2

@whitehorsetechn

Greeting, I have understood your Xilinx DDR3 controllers development for Frame buffer task and can do it with your 100% satisfaction. Please ping me for more discussion. I have more than 5 years of experience in Electrical Engineering, Electronics, FPGA, Microcontroller, Verilog / VHDL

$2,500 USD in 30 days