IC Physical design engineer

6 years experience in full IC physical design cycle using Cadence Encounter/Innovus/Tempus from chip floorplan, clock tree synthesis to place and route and timing closure

Hello, I am a digital design engineer with experience +5 years in writing RTL code(Verilog/VHDL). I have also taken ASIC design diploma which concentrated on Design compiler (For synthesis) and Cadence Encounter (For F More

Hi there, Reading your job desciption, I feel like I can do this. I'm experienced in Verilog FPGA development, digital/analog electronics, working with Linux for several years, and other soft skills such as teamwork an More

Dear Client. How is it going? I have just read your job description and your project is really interesting to me. I have many experiences working for 7+ years with Circuit and PCB design, FPGA design using Verilog/VHD More

Hello HandsAndBrains,   We have 20 years of strong experience in Perl, Python, Verilog / VHDL, UNIX, Circuit Design, as a result, we can successfully complete this project.   Please, review our profile here: https: More

Hello, I hope this finds you well. I have just seen your project requiring; Perl Python Verilog / VHDL UNIX Circuit Design I believe that my 8-year experience in this field is what you need right away. Avoid the hea More

Hello, thank you for your job posting. As a senior electrical engineer, I have a lot of experience in PCB design and firmware development. Design circuits and PCB: Altium, Eagle, KiCad, Allegro & OrCAD, PADs. The serv More

Hi, I am a senior Python (Django, Flask) developer with 10 years of total experience. I work remotely with customers from Europe and the States for nearly 5 years. I have acted as software architect and tech lead. I us More

Hi there, I'm an engineer in a hardware development company in Shenzhen, China. Can we talk about your project? Best regards, Penny

Hello, I have most of the skills you mentioned. I have experience of 17 years in electronic design/ Including FPGA and circuit design. I use scripts all the time FPGA (simple and complex design) using vhdl (on Xilinx More

I have 15 years of Work Experience in ASIC / FPGA Design at organizations like "OpenSilicon"([login to view URL]) and Power Down Semi ([login to view URL]). At PowerDownSemi, closing the P&R of TSMC 65nm ASIC. Th More