Hi, Verilog HDL expert here with 15+ years experience (since early 1998). 36 yo, really old in this field and experienced ^_^ Have designed more than 20 CPUs and overall 125+ custom designs including FFT, DCT, motion estimation, motion compensation, MSF receiver, DCF77 receiver, bus encoders, multiple ASIPs/CPUs incl. the research ByoRISC processor. Guaranteed quality of work and delivery within one work week (7 calendar days).