cardinal processor new - open to bidding

Hi, I had done MS in Digital Signal Processors and Digital Design. Also I had around 8 years of industrial experience in the field of FPGAs and VerilogHDL/VHDL programming. I had worked on several projects related to Verilog HDL. You can contact me with full confidence.

I have designed thomosulo algorithm processor with stalling and forwarding process. I can designed this processor along with test-cases. I have 5 years of experience in verilog and digital design. its should done.

The test bench would be a structured test bench including: 1. Parameter definitions 2. DUT Input regs 3. DUT Output wires 4. DUT Instantiation 5. Initial Conditions 6. Test Vectors 7. Debug output Our documentation will provide you a clear list of all register declarations, variables and other constructs used in the coding. To give a further proposal, we would need more information on the nature of DUT that you need to be tested.

I have worked on many FPGA projects like image processing and object detection ,MIL-STD 1553 and ARINC protocol. I have a good working exprience on design and verification .So I can provide you a good design with test code