1- project layout , 2- test using irsim
A VLSI design i need to implement using (magic) and test it using (irsim) it's a circuit i design it and the phase 2 i want it is to implement and test the design all the information will be in the direct message i have a pdf file that learn you everything and the phase 1 that i make it .
Assalam o alaikum !!! I am looking for expert electrical engineers in following subjects of electrical & electrical engineering: 1) Digital Signal Processing (Matlab) 2) Electronic Design (Multisim/Proteus) 3) VLSI Techniques (Cadence PSPICE) 4) Digital Instrumentation and simulations (LabVIEW) 5) Communication (Matlab) 6) Mobile and Wireless Communication (Matlab) 7) Satellite Communication (Matlab) 8) Microwave Communication System 9) Multimedia Communication & IoT I am hiring experts from PAKISTAN only. Thank you
Hello if you have experience of Cadence software then i have some projects you would like to work . s per discussion with my guide I have finalized my project, below are the requirements Design and implement A 4 x 4 bit Vedic Multiplier 90nm technology 2. Implementation using 2 technologies a. CMOS. 3. Both design implementation to be done on cadence virtuoso software and layout for both cmos and mGDI techniques both simulations in terms of PDP,area, speed, overall performance parameters, delay.
Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000 to 0x801F. 2- You can read and write one byte at a time. 3- The are special output signals that are required. They are listed in the table below
Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000...at a time. 3- The are special output signals that are required. They are listed in the table below. -------------- Requirement: Phase 1:Part 1: Verify the design using a logic design tool and an HDL tool (VHDL or Verilog) using structural method Part 2: List in a table the required components with their respective input and output labels. --- Phase 2: Part 3: Implement your design using Magic VLSI layout tool to generate your project layout Part 4: Test your design using irsim to simulate your project. phase 1 should be by Sunday Deliverables: TBD
Assalam o alaikum !!! I am looking for electrical engineers having strong background in following areas 1) Control System Design (Matlab simulations) 2) Virtual Instrumentation and Simulation (LabView) 3) VLSI Techniques (orCAD PSpice & Cadence) 4) Microwave Communication Systems 5) Multimedia Communication & IoT 6) Telecommunication Engineering 7) High Voltage and Condition Monitoring I need experts for long term basis, I highly encourage new freelancers / fresh graduates to apply. If you are a third party managing a team of experts then please do not place your bid.
Design an inverter to get NMH=NML and VM = VDD/2. Obtain the noise margins and the propagation delay time by simulating the layout and plotting dynamic and static characteristics. (Load the inverter under test with an identical inverter before running the simulation.) Then design an oscillator by placing 5 inverters designed above in a closed loop. Run a simulation and plot the waveform at the output of each node. Compare the frequency of the generated signal with the expected frequency based upon the obtained tp of the inverter. Submit the layout, results of the simulation. software to use is Microwind.
Computer Communication (Network of VLSI Switching Elements) like Produce a discrete event simulation of a network
...scrambler-descrambler OR encoder-decoder) and makes sure that Both pairs are working together fine. 5) Check the results in log/waves, and create regression commandline to make sure they can be rerun in future. Detailed Requirement :- 1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experience either in RTL Design or TB/Verification. 2) Experience in VLSI - ASIC/FPGA design with following skillset - a) Verilog, System Verilog, b) Perl, Bash, Make c) working in Unix/Linux Environment and Vim/gvim 3) Following are domain expertise - a) For junor engineers - Intermediate to efficient capability in skillset above. Added advantage is experience in RTL-design and/or verification experience of small to medium sized blocks. b) For...
for the project 2. Video demonstration 3 Explanation of the project and research paper
In order to improve my skills I need this project in order to design an NMOS and PMOS transistor. As a next step I need to use them to design an inverter. Everything should be simulated in the VLSI layout for the MOS transistors and for the inverter. Several figures to clearly show each layer would be necessary. In order for me to understand your work I need a short report (less than 10 pages ) where discusing the voltage supply required to make the inverter work and its input and output voltages for logic 1 and logic 0 levels, as well as the power requirements and switching frequency of the inverter. If there are any questions do not hesitate to contact me :)
I need someone who understands VLSI Digital Electronics
Hi, We are looking for part time trainer who can train in VLSI.. interested candidates please send your details [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms and Conditions] Thanks Team Vigos