Verilog vhdl jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    4,788 verilog vhdl jobs found, pricing in GBP
    VHDL Ended

    The purpose of this project is to develop a device that can be used in combination with a normal phone to expand its capabilities to use it for VOIP and/or Skype services. The VOIP/Skype interface...VOIP/Skype interface should be configurable over the Ethernet interface and can be used from the phone by starting a call using special characters like "**" or "*##". Since the phone now needs to deal with multiple lines, there should also be proper handling to deal with e.g. two incoming calls etc. To make this project I'm using Altera DE2-115 board to implement a voice over IP phone on FPGA using VHDL coding. The final goal is to use SIP and other protocols for VOIP communication such as rtp, g.711, TCP, UDP and Ethernet. And other protocols for the board itsel...

    £1096 (Avg Bid)
    £1096 Avg Bid
    1 bids

    actually am doing my in vlsi (spl).and i need to do the project what i uploaded here in vlsi implementation.i.e first of all i need to write code in matlab and convert it into verilog and dis verilog code need to dump in fpga kit

    £591 (Avg Bid)
    £591 Avg Bid
    1 bids

    Hello everyone We want project design of fast fourier transform using vhdlof radix 4, N point FFT architecture and also you have to submit professional 100-120 page report and 15-20 page ppt slides on it and you do not have to submit any hardware but you have to submit vhdl cod as well as all hardware implementation detail so we can implement hardware here so happy bidding

    £101 (Avg Bid)
    £101 Avg Bid
    9 bids

    I need a VHDL code that counts from 0 to 9 and show the output both on character LCD and on LEDs as binary numbers the counter should count every 1 second

    £603 (Avg Bid)
    £603 Avg Bid
    16 bids

    Write VHDL code in Xilinx ISE for Spartan 3. Program should add and substract 4-bit positive and negative binary numbers. Subtract is allowed if first number is bigger than second. If that condition ain't satisfied turn on 'g' segment on 7-segment display. Input combinations are set up with switches and result is shown on 7-segment display.

    £9 / hr (Avg Bid)
    £9 / hr Avg Bid
    10 bids

    Program should add and substract 4-bit positive and negative binary numbers. Subtract is allowed if first number is bigger than second. If that condition ain't satisfied turn on 'g' segment on 7-segment display. Input combinations are set up with switches and result is shown on 7-segment display.

    £2 - £24 / hr
    £2 - £24 / hr
    0 bids

    I have a project which is to design an alarmclock cum stop watch by using Xilinx board and VHDL time could be set by a numeric keypad or keyboard and display on the LCD. I have already bought the Xilinx board which the model is Spartan-3A. I am looking for a person who can do it.

    £325 (Avg Bid)
    £325 Avg Bid
    15 bids

    i have attached a file that shows the c-program coding that needs to developed. I have done the state diagram entry and TFF equations part. but I need help building the Verilog part. the aim of the part is to generate verilog HDL code from the state diagram info taken in the c-programming. its Urgent.

    £121 (Avg Bid)
    £121 Avg Bid
    9 bids

    you have it in my email 200 usd within 24 hours if more it will be 150 usd

    £158 (Avg Bid)
    £158 Avg Bid
    1 bids

    Mastermind desing with verilog. Details are on the file please read it

    £141 (Avg Bid)
    £141 Avg Bid
    5 bids

    Its a digital clock using VHDL all data included in file Its basically works on the fundamental of clock feq.1 hz clock generation using clock through this we get 1 sec of pulse and by using 1 sec of time period,we can calculate the sec--min--hour. Its include by using positive edge of clock pulse we count upto 50000000 count and through this we change the status of the clock...so when count get 50000000 then half of clock period get completed..so when 50000000*2 get posedge of clock and through this we get 1 second of time... file: test bench ///////////////////////////////// Its a digital clock using VHDL all data included in file Its basically works on the fundamental of clock feq.1 hz clock generation using clock through this we get 1 sec of pulse and

    £42 (Avg Bid)
    £42 Avg Bid
    12 bids

    I am looking for somebody who can build SIC/XE processor simulator for format 2 and 3 with same length by adding 00 in the beginning of format 2 instruction

    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    I am looking for somebody who can build SIC/XE processor simulator for format 2 and 3 with same length by adding 00 in the beginning of format 2 instruction

    PHP
    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    I am looking for somebody who can build SIC/XE processor simulator for format 2 and 3 with same length by adding 00 in the beginning of format 2 instruction

    PHP
    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    I am looking for somebody who can build SIC/XE processor simulator for format 2 and 3 with same length by adding 00 in the beginning of format 2 instruction

    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    Hi, I am looking for a good Verilog coder who can code some basic logic design. PM me if you would like to know more. I would like it done by Thursday so if you take the project, you will be given two days at most to complete it. I prefer it to be done in a day. It shouldnt take more than an hour or two if you're familiar with Verilog. Thank you

    £263 (Avg Bid)
    £263 Avg Bid
    12 bids

    This project is on VHDL need to be professional in VHDL the information is given in the attached in the document. 1. Modify and utilise the provided behavioural model for a 4-bit register, to compile, simulate and verify correct functional operation of an 8-bit device.( behavioral model for a 4-bit register provided at the end of the page) 2. Modify the dataflow architecture (figure 1) to facilitate the implementation of the complete instruction set (table 1). Note: special attention will need to be given to the inclusion of a shifter and execution of the increment and decrement instructions. 3. Design and individually simulate behavioural VHDL models for the dataflow components. Combine structurally to define the complete dataflow

    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    I am in need of a fully working design of an FPGA based oscilloscope, Must be at least 20 Mhz and bidder must provide full analog front end circuit and VHDL code to view the output on a PC via USB or Ethernet. Work must be your own.

    £355 (Avg Bid)
    £355 Avg Bid
    2 bids

    We need a pipelined verilog datapath that is formatted to MIPS ISA. We can provide you a non pipelined datapath to use as a reference. We have also included a non-pipelined and pipelined image of what the datapath should look like. It will need to be able to input MIPS assembly code into the program via a .txt file. Additionally, we need this datapath and assembly code to be able to be synthesized on a Spartan 3E FPGA board. Overview: -Design a pipelined version of the datapath - Synthesize the design - Run it on FPGA board using our assembly code - Use the LCD of the FPGA board to display the coordinates of the block with the minimum SAD.

    £379 (Avg Bid)
    £379 Avg Bid
    10 bids

    To utilise structural and behavioural VHDL to model and simulate an 8-bit processor capable of implementing the attached instruction set. VHDL have to be used. For designing need multisim.

    £79 (Avg Bid)
    £79 Avg Bid
    2 bids

    Hi, I need a state machine that controls the Wiznet chip W5300 for UDP or Ethernet communication. The scope is to send data on ethernet at (at least) 10 Mbit/s. The state machine should be in Verilog (not VHDL) targeting an FPGA. Further datails in PM.

    £84 (Avg Bid)
    £84 Avg Bid
    6 bids

    I need you to do the following parts in the previous VHDL report that you have done for me . Before I hire you please agree to me that you will do all the required and amend them the report where also you will need to amend the result and discussion parts . 1)Do error codes control based in the Linear Sequential System and amend it on the report and in the code in the 7/4 decoder and in the 15/11 decoder and the generic code. Please you must to use error codes check in the 7/4 decoder, 15/11 decoder and in the generic code . please amend it in the report and in the codes . 2) Do full LSS simulating the 7/4 decoder using TIMING analysis .It is in section 3b .You have to do it in the code and in the report. 3) You nee to You write about Timing and what is the difference betwe...

    £79 (Avg Bid)
    £79 Avg Bid
    1 bids

    Using VHDL language, QUARTUS II software and ALTERA DE2 board, you should design, simulate, and implement an 8-bit ALU circuit. This circuit will take two 8-bit unsigned binary numbers, operate on them, and display the result. ? First, the 7-segment display should display "S0" to indicate "State 0". When a push button on the DE2 board (e.g. KEY1) is pressed, the 8-bit value provided on the Toggle Switches SW7 to SW0 (operand1) should be stored in a register. Note that SW7 is the MSB and SW0 is the LSB. ? The 7-segment display should then display "S1" to indicate "State 1". When the push button is pressed again, the 8-bit value provided on the Toggle Switches SW7 to SW0 (operand2) should be stored in a register. ? The 7-segment display sh...

    £30 (Avg Bid)
    £30 Avg Bid
    2 bids

    I need a verilog coder to code a simple ALU type operation. test bench, guide, inputs, specifications, will be given. You just have to code verilog file. I wil tell you details in message, but code I require is simple. So budget is not very high. I give preference to people with lower bid and good history/ratings. THIS is NOT VHDL CODING. Only, people with experience in verilog should apply. PLease tell me your experience is verilog and I wil provide you more details about project. If you can send me any of verilog file you have coded ; I will look and your skill/knowledge and will give preference to people who can provide example of their code. Deadline is 7-10 days.

    £52 (Avg Bid)
    £52 Avg Bid
    8 bids

    Hi, I need a person who can do a verilog job for me. More details will be provided in PM. If you previous work sample on Verilog then it would be plus. Would be waiting for your bids. Thanks

    £86 (Avg Bid)
    £86 Avg Bid
    11 bids

    Hi, I need a person who can do a simple verilog job for me. More details will be provided in PM. If you previous work sample on Verilog then it would be plus. Would be waiting for your bids. Thanks

    £53 (Avg Bid)
    £53 Avg Bid
    8 bids

    Hi, I need a verilog HDL code for a simple project, the project is as follows: you start off as a single blue square on the bottom of the screen(background black), then once the game starts, blocks(red squares) start falling from the top of the screen and you use KEY[1]and Key[2] on the DE2 board as controls to move your square right/left to dodge the falling blocks. if you get hit by a falling block the game terminates and goes back to it's original state(a single blue square at bottom of screen). the below is the vga adapter we use module part1(SW,KEY,CLOCK_50,VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK,LEDR); input CLOCK_50; input [17:0] SW; input [3:0] KEY; output [17:0]LEDR; output [9:0] VGA_R; output [9:0] VGA_G; output [9:0] VGA_B; out...

    £120 (Avg Bid)
    £120 Avg Bid
    3 bids

    Hi there, I am looking for a digital designer with experience in VHDL, preferrable on ASIC, but FPGA will be considered as well. I am working on a complex project that will last a long time and I need help with development. Experience with Ethernet, LVDS or DDR would be a plus. I will first start with a small task to ensure that everything goes fine. Once that ends I will provide more and more work. Thank you. Regards, Nick Keywords: VHDL, digital design, electronics, VLSI, ASIC, FPGA

    £9 / hr (Avg Bid)
    £9 / hr Avg Bid
    26 bids

    Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved face data...

    £316 (Avg Bid)
    £316 Avg Bid
    14 bids

    Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved face data...

    £280 (Avg Bid)
    £280 Avg Bid
    4 bids

    To create a "checker" in a Network Interface. 1. Checker will collect 32 bits data from 8 deserialisers. (eg A1 ~A8) 2. Checker will collect 32 bits data from 3 Collectors. (eg C1~C3) 3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 =...Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release data, if C3 = None delete C3) 5. continue process. I attached a picture and original source code for Network interface. "Checker " is to target on at the Receiver. Preferably using Xilinx in VHDL...

    £222 (Avg Bid)
    £222 Avg Bid
    1 bids

    To create a "checker" in a Network Interface. 1. Checker will collect 32 bits data from 8 deserialisers. (eg A1 ~A8) 2. Checker will collect 32 bits data from 3 Collectors. (eg C1~C3) 3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release ...3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release data, if C3 = None delete C3) 5. continue process. I attached a picture and original source code for Network interface. "Checker " is to target on at the Receiver. Preferably using Xilinx in VHDL...

    £222 (Avg Bid)
    £222 Avg Bid
    1 bids

    I am running a big project and am currently time constrained to implement the Ethernet connection. This is a fairly easy project for someone with expertise in Verilog. The deliverables are as follows -Verilog code to run on a Spartan 6 Atlys Board - (xc6slx45) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 100mbs (1Gbps support would be nice but not a must) -Support a multicasting protocol (In that if I wanted to send data to 3 recepients out of 5 in the network, I should be able to do it easily) -Support for broadcasting (be able to make the system send the data to all recepients in the network when needed) -there are existing IPcores that offer a starting point and I would suggest tha...

    £302 (Avg Bid)
    £302 Avg Bid
    3 bids

    1) Design and build a 8-bit adder using structural or behavioral verilog code. Account for an initial carry-in bit. 2) How to start ? 3) Verilog code in either structural or behavioral format Test bench and simulated waveforms showing the inputs and outputs. Add the 8-bit numbers: 50 + 120 with initial carry in of 0 80 + 75 with initial carry in of 1 225 + 142 with initial carry in of 0 180 + 75 with initial carry in of 1

    £58 (Avg Bid)
    £58 Avg Bid
    13 bids

    I'm working on the VHDL programming for my thesis and one of my task is to write the code for a simple Hello program. The message on the LCD screen should be able to blink on toggling one of the switches. I'm not sure how to make a start on this. Also, there are few things I would like to ask before starting working on it. For further information please contact me on this website. Thanks

    £24 - £32
    £24 - £32
    0 bids

    Create a project in Xilinx ISE that uses the OpenCores tri-mode MAC that works on the Xilinx SP605 Spartan 6 LX45 evaluation board. You can use one of the existing Xilinx demo projects as a base, or anything t...can be a peripheral that just replaces the existing Xilinx peripheral in an EDK design, or it could just be a stand-alone project. Basically, for anyone that already has already used the OpenCores tri-mode MAC at a gigabit on the SP605, this project is probably just a matter of exporting one of your test projects. The project MUST be in VHDL, sorry Verilog not accepted under any circumstances (except for any OpenCores code that is wrapped with VHDL). No payment up front, but 25% payment considered before delivery if you provide a VNC view of the code ...

    £624 (Avg Bid)
    £624 Avg Bid
    6 bids

    Need to evaluate the FPGA prototyping board Altera cyclone 2 DE1 to design a voice recorder. Design the project using design should be able to record a minimum of 1 minute of audio input and playback clearly through the on-board speaker or an external speaker. In need of the VHDL programme codes and a Report on the analysis and how the design is done.

    £339 (Avg Bid)
    £339 Avg Bid
    4 bids

    Xilinx ISE Project – VHDL design for Virtex 6 FPGA The task is to create a Xilinx ISE project to work with the Xilinx ML605 development board and a mating DAC board. The DAC board comes from a company called 4DSP, model FMC204. See Handbook for FMC204 board attached. The ML605 from Xilinx is a development board for the Virtex 6 FPGA. See The FMC204 board plugs into the ML605 via the high density FMC connector. The project is to generate a simple sine wave at 28MHz in the FPGA and have the DAC board produce 4 analogue output signals. The clock on the DAC board is to run at 112Mhz and provide a reference clock to the FPGA. The DAC sample frequency is also 112Msps. There are

    £473 (Avg Bid)
    £473 Avg Bid
    3 bids

    1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

    £686 (Avg Bid)
    £686 Avg Bid
    5 bids

    1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

    £1124 (Avg Bid)
    £1124 Avg Bid
    6 bids

    I want to protect my IP cores, targeting Xilinx FPGAs, by using a 1-Wire EEPROM with SHA engine. It is explained in Xilinx application note xapp780 how it can be made. The vhdl source codes as well as picoblaze processor source codes for the xapp780 can also be downloaded from the Xilinx website. The problem is that the xapp780 is for DS2432 EEPROM from Maxim IC. However, I want to use DS28E01-100 EEPROM instead. I compiled the sources but the design is not working with DS28E01-100 EEPROMs. Some more points: 1 - You have to change the xapp780 sources so that it it works with DS28E01-100 EEPROM. 2 - We need 2 designs as it is in xapp780, loader and tester. Loader programs the EEPROM with our security key. Tester checks if the SHA keys are matching. 3 - Target FPGA is X...

    £491 (Avg Bid)
    Featured
    £491 Avg Bid
    6 bids

    You need to model a "Combination lock" state machine that activates an "unlock" output when a certain binary sequence received: Please see the attached file ## Deliverables see attached

    £40 (Avg Bid)
    £40 Avg Bid
    2 bids

    We are looking for someone who has worked with the Xilinx Endpoint Block for PCI Express before and sets up an example project for us. ## Deliverables It does not matter what variant of the endpoint block you have used before, but you must have developed code to control it your self, not just instanciated some third party wrapper like EZDMA. Our development will be done in VHDL. If you have a software setup that allows you to simulate the endpoint block together with the GTP we can outsource also the validation to you.

    £41 / hr (Avg Bid)
    £41 / hr Avg Bid
    2 bids

    I need VHDL code written for a Nexys2 Board from Digilent, Inc. that focus only on the refresh rate of the VGA Monitor displaying in the color black and White. Each color should be connected to a switch so I can test good and bad refresh rates for each separate color on the monitor. I will need the syntax written for the UCF file to correctly connect to the Nexys2 board to perform testing of the code. I will need instructions on how to manually change the refresh rates in the code myself so I can use Xilinx ISE Design Suite 13.1 to generate a bit file that will be loaded to the board with Adept Software. I need to be able to set good and very bad refresh rates to record for my research for each color.

    £137 (Avg Bid)
    £137 Avg Bid
    9 bids